A continuous-rate Clock Data Recovery(CDR) circuit is proposed, which covers a data rate of 500 Mbps to 4 Gbps. The proposed CDR，implemented in 130 nm Complementary Metal Oxide Semiconductor(CMOS)，is based on phase interpolation and utilizes digital voter and phase control logic instead of charge pump and analog filter, which is meaningful to transplantation between different technologies. To reduce the frequency range of the clock of Phase Lock Loop(PLL) outputs and avoid the Phase Interpolator(PI) getting into the nonlinear region，multimode is designed to limit the frequency range of the sampling clock only from 500 M to 1 GHz. The PI realizes an accuracy of 7 bit and a good linearity, while the peak-to-peak jitter of the recovered clock of is about 25.6 ps at 4 Gbps. The CDR realizes a BER<10-10 and is able to track a maximum frequency offset of ±976.6 ppm between the input data and the sampling clock. The power consumed by the proposed CDR is 13.28 mW/Gbps. A 5 mm2 test chip is also fabricated, where the CDR core occupies 0.359 mm2 of area.