引用本文:[点击复制]
[点击复制]
【打印本页】 【在线阅读全文】【下载PDF全文】 查看/发表评论下载PDF阅读器关闭

←前一篇|后一篇→

过刊浏览    高级检索

本文已被:浏览 703次   下载 60  
一种基于FPGA的新颖的高容错加法器的设计
0
()
摘要:
为了解决传统TMR结构的CMFs失效问题,根据加法器的结构特点提出了操作数循环移位及取反算法(TOIR-SO)。此方法相对于传统的TMR结构能够使TMR系统失效率降低47%。同时对逻辑运算的基本单元全加器进行了改进,改进后加法器中任何一个失效只能影响一位"和"结果而不会对其它位产生影响从而进一步提高了加法器的容错能力。
关键词:  集成电路设计  三模冗余设计  操作数循环移位及取反容错  同部件失效问题  全加器  
DOI:
基金项目:
Novel Fault-Tolerant Adder Design Basing on the Triple Module Redundancy System
()
Abstract:
We propose TOIRSO which is for resolving the CMFs in the TMR systems.Comparing to the conventional TMR system,the invalid rate of system reduces 47%.And a full adder prototype has been developed.The fault-tolerant ability of the adder using this kind of full adder is enhanced.Because one faulr-mahing has only an effest on the resner of one bit and no influence to the other bits.
Key words:  integrated circuit design  triple module redundancy(TMR)  TOIRSO(Tolerating by Inverted and Rotate Shifted operands)  common mode failures(CMFs)  full adder  

用微信扫一扫

用微信扫一扫