As the size of Field-Programmable Gate Array(FPGA) has surged rapidly, the deteriorative runtime of Computer-Aided Design(CAD) tools has become a major concern. Routing is one of the most time-consuming stage in CAD process, while introducing parallel routing algorithm could be an effective way to cut the runtime. A multithread timing-driven routing technique based on this idea is proposed in this paper. In the parallelization approach, nets are sorted according to their fan-out amount sequence firstly, then the sorted nets are averagely assigned into threads and all the threads are executed concurrently. Using this method, the total wire length and critical path delay are increased by 2.58% and 1.78% respectively, which means the routing quality is well preserved. However, in terms of runtime, it wins approximately 2.46× speedup versus the widely used Versatile Place and Route(VPR) in the case of 8 threads.