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计算机工程 ›› 2007, Vol. 33 ›› Issue (03): 231-233. doi: 10.3969/j.issn.1000-3428.2007.03.084

• 工程应用技术与实现 • 上一篇    下一篇

适用于空间环境下的FPGA容错与重构体系

徐 斌1,2,王贞松1,陈冰冰1,章立生1   

  1. (1. 中国科学院计算技术研究所,北京 100080;2. 中国科学院研究生院,北京 100080)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-02-05 发布日期:2007-02-05

Architecture for Fault-tolerance and Reconfiguration of FPGA in Aerospace

XU Bin1,2, WANG Zhensong1, CHEN Bingbing1, ZHANG Lisheng1   

  1. (1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080; 2. Gradute School, Chinese Academy of Sciences, Beijing 100080)
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-02-05 Published:2007-02-05

摘要: FPGA极大地提高了电子系统设计的灵活性和通用性,被广泛地应用在各个领域。在空间环境中,FPGA 容易受到SEU的影响而导致内部逻辑的紊乱,系统重构与故障恢复也比较困难。该文提出了一种在星载环境下,使用CPLD对FPGA进行基于错误诊断的容错体系结构设计,兼顾到了系统重构与故障恢复,在实验中取得了较好的效果。

关键词: 空间环境, SEU, FPGA容错, CPLD, 重构

Abstract: FPGA greatly improves the flexibility and universality of electronic system, and is widely used in various fields. However FPGA is sensitive to SEU in aerospace which leading to the destruction of internal user logic. Updating and fault-recovery of system-level are also quite difficult. Based upon this, this paper presents an architecture that detects and corrects the fault of FPGA based upon error diagnosis with a CPLD in aerospace. Meantime, this architecture can also implement reconfiguration and fault-recovery at system-level.

Key words: Aerospace, Single event upsets(SEU), FPGA fault-tolerant, CPLD, Reconfiguration