| 面向5G标准的低延时LDPC编码器设计 |
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| 引用本文： | 李赛,周林,唐益多,陈辰,傅玉青,贺玉成. 面向5G标准的低延时LDPC编码器设计[J]. 信号处理, 2020, 36(2): 224-232. DOI: 10.16798/j.issn.1003-0530.2020.02.009 |
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| 作者姓名： | 李赛 周林 唐益多 陈辰 傅玉青 贺玉成 |
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| 作者单位： | 华侨大学厦门市移动多媒体通信重点实验室 |
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| 基金项目： | 国家自然科学基金(61901182,61302095);福建省自然科学基金(2018J01096,2018J05105);泉州市科技计划项目(2018C108R);华侨大学研究生科研创新基金资助项目(18014082024)。 |
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| 摘 要： | 针对 5G 标准中对低延时和编码灵活性的要求， 本文提出了一种高并行度的低密度奇偶校验(Low-Density Parity-Check， LDPC)码编码算法并设计了相应的硬件结构。 编码算法对校验位的计算流程进行了改进， 通过将对应 5G 标准中校验矩阵单对角和双对角结构的不同编码步骤并行化提高了运算速度。 在硬件结构上一方面设计了多路并行的运算结构通过同时求解多个编码步骤降低了处理时延， 另一方面灵活的结构设计使其可以有效地支持5G不同场景下对码长和码率的要求， 并通过分组计算校验位实现了对递增冗余的HARQ (IR-HARQ)方案的支持。仿真结果表明，在 200 MHZ 的系统时钟频率下， 本设计的信息吞吐量可达 35Gbps。
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| 关 键 词： | 低密度奇偶校验码编码器 多速率 准循环 第五代移动通信技术(5G) 现场可编程门阵列(FPGA) |
| 收稿时间： | 2019-11-21 |
A Low Latency LDPC Encoder for 5G |
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| Li Sai,Zhou Lin,Tang Yiduo,Chen Chen,Fu Yuqing,He Yucheng. A Low Latency LDPC Encoder for 5G[J]. Signal Processing(China), 2020, 36(2): 224-232. DOI: 10.16798/j.issn.1003-0530.2020.02.009 |
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| Authors: | Li Sai Zhou Lin Tang Yiduo Chen Chen Fu Yuqing He Yucheng |
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| Affiliation: | Xiamen Key Laboratory of Mobile Multimedia Communications, National Huaqiao University |
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| Abstract: | In order to meet the requirements of low-latency and flexibility coding in 5G system,an efficient High-Parallelism Encoding(HPE) algorithm and the related hardware implementation for 5G Low-Density Parity-Check(LDPC) codes are proposed.The different operations corresponding to the dual-diagonal structure and diagonal structure in check matrix are processed in parallel to increase the calculation speed in HPE algorithm.To match the HPE algorithm,the Encoding Unit is designed into a multi-channel structure which can process the parallel steps in HPE simultaneously in the proposed encoder to achieve low encoding latency with acceptable hardware resources consumption.In addition,the flexible structure ensures the proposed encoder can switch among different rates over the complex channel conditions and calculate parity bits in goups to satisfy the requirement of rate matching and IR-HARQ scheme in 5G standard.With a maximum clock frequency of 200 MHz,the implementation results into Field Programmable Gate Array(FPGA) device show that the proposed low latency LDPC encoder is capable of reaching a speed of 35 Gigabits per second(Gbps). |
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| Keywords: | encoder low latency Low-Density Parity-Check codes 5th generation mobile networks Field Programmable Gate Array |
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