实时高精度麦克风阵列数据采集系统 |
| |
引用本文: | 胡德孟,何培宇,张 勇,潘帆,罗胡琴. 实时高精度麦克风阵列数据采集系统[J]. 信号处理, 2013, 29(10): 1362-1367 |
| |
作者姓名: | 胡德孟 何培宇 张 勇 潘帆 罗胡琴 |
| |
作者单位: | 四川大学电子信息学院 |
| |
基金项目: | 国家自然科学基金(61071159) |
| |
摘 要: | 针对麦克风阵列语音增强系统对高精度和强实时性数据采集的需要,设计并实现了一种基于FPGA的麦克风阵列数据采集系统。其主要包括数模转换模块、数据接收处理模块和以太网控制模块3部分,实现了对16路语音信号的高质量采样和传输。系统中,将UDP数据报协议用硬件编程语言verilog在FPGA上实现,与基于操作系统的TCP/IP协议族实现UDP协议相比,大大提高了资源利用率。测试结果表明,系统能完成16路语音信号的高精度、高可靠性实时采集和传输,以太网传输速率达2.3MByte/s,满足了麦克风阵列语音增强系统的研究需要。
|
关 键 词: | 麦克风阵列 FPGA UDP协议 数据采集 |
收稿时间: | 2013-04-30 |
Real-time High-precision Microphone Array Data Acquisition System |
| |
Affiliation: | College of Electronics and Information Engineering, Sichuan University |
| |
Abstract: | For microphone array speech enhancement system of high precision and strong real-time data acquisition needs, a FPGA-based microphone array data acquisition system has been designed and implemented. The system which mainly includes digital-to-analog conversion module, data receiving-processing module and the Ethernet control module achieved high-quality sampling and transmission rate for 16-channel-voice signals. In this system, UDP datagram protocol was implemented on FPGA by using Verilog which is a hardware programming language. Compared with the UDP protocol implemented on the TCP/IP protocol family of operating system, the resource utilization is greatly improved. The test results show that the system can collect and transmit the 16-channel-voice signals with high-precision, high-reliability real-time acquisition, and the Ethernet transmission rate is 2.3MByte/s , which met the research needs for microphone array speech enhancement system. |
| |
Keywords: | |
|
| 点击此处可从《信号处理》浏览原始摘要信息 |
|
点击此处可从《信号处理》下载免费的PDF全文 |
|