| 神经网络正弦信号发生器 |
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| 引用本文： | 王海宇,谢利理,王杉.神经网络正弦信号发生器[J].计算机工程与应用,2019,55(16):259-264. |
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| 作者姓名： | 王海宇 谢利理 王杉 |
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| 作者单位： | 西北工业大学 自动化学院,西安,710129;西北工业大学 自动化学院,西安,710129;西北工业大学 自动化学院,西安,710129 |
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| 摘 要： | 针对正弦信号发生器设计中,直接数字频率合成技术存在相位截断误差的问题,以神经网络为技术基础,以FPGA为硬件核心,提出了一种新型的高频正弦信号发生器设计方案,有效克服了上述问题。阐述了这种方案的工作原理、电路结构以及设计思路和方法。经过设计和仿真测试,系统的主时钟频率可以达到95 MHz且不占用ROM存储空间,输出的正弦信号为2.5 MHz时,输出信号的杂散抑制为80 dB,可见该方案资源占用率低,无相位截断,输出信号杂散小且输出频率较高。
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| 关 键 词： | 正弦信号发生器 神经网络 现场可编程门阵列(FPGA) 直接数字频率合成 |
Neural Network Sinusoidal Signal Generator |
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| WANG Haiyu,XIE Lili,WANG Shan.Neural Network Sinusoidal Signal Generator[J].Computer Engineering and Applications,2019,55(16):259-264. |
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| Authors: | WANG Haiyu XIE Lili WANG Shan |
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| Affiliation: | School of Automation, Northwestern Polytechnical University, Xi’an 710129, China |
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| Abstract: | Aiming at the problem of phase truncation error in direct digital frequency synthesis technology when designing the sinusoidal signal generator, this paper proposes a new design scheme of high frequency sinusoidal signal generator, which is based on neural network technology and uses FPGA as the hardware core. This scheme effectively solves the problem above. This paper expounds the working principle, circuit structure, design ideas and design method. Through design and simulation test, the master clock frequency of the system can reach 95 MHz and the system does not occupy storage space. When the output sinusoidal signal is 2.5 MHz, the spurious suppression of the output signal is 80 dB. These show that the scheme has low resource occupancy rate, no phase truncation, small spurious output signal and high output frequency. |
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| Keywords: | sinusoidal signal generator neural network Field Programmable Gate Array（FPGA） direct digital frequency synthesis |
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