| 大规模高帧频读出电路高速数据传输模型研究 |
| |
| 引用本文： | 叶联华,刘煦,李云铎,黄松垒,黄张成.大规模高帧频读出电路高速数据传输模型研究[J].红外技术,2022,44(1):66-72. |
| |
| 作者姓名： | 叶联华 刘煦 李云铎 黄松垒 黄张成 |
| |
| 作者单位： | 1.中国科学院上海技术物理研究所 传感技术联合国家重点实验室, 上海 200083 |
| |
| 基金项目： | 上海市自然科学基金(19ZR1465500)。 |
| |
| 摘 要： | 本文针对大规模高帧频读出电路的数字信号输出建立了高速数据传输模型。首先由集总参数模型得到传输电路3 dB带宽及响应时间常数与各器件参数之间的关系，指明了输出级MOS管的尺寸及传输线负载是决定高速时域响应特性的关键参数。进一步采用分布参数模型，利用Elmore延时模型更精确地确定了响应时间常数的数学解析式，获得了可使带宽最大化的输出级尺寸的最优设计。仿真结果表明，在典型的64×64面阵功耗和面积约束条件下，优化后传输门和复合逻辑门两种三态传输电路的输出3 dB带宽分别可达293 MHz和395 MHz。
|
| 关 键 词： | 大规模高帧频读出 数据传输模型 Elmore延时模型 |
| 收稿时间： | 2020-12-07 |
Research on High-Speed Data Transmission Model of Large-Format High-Frame-Rate Readout Integrated Circuit |
| |
| YE Lianhua,LIU Xu,LI Yunduo,HUANG Songlei,HUANG Zhangcheng.Research on High-Speed Data Transmission Model of Large-Format High-Frame-Rate Readout Integrated Circuit[J].Infrared Technology,2022,44(1):66-72. |
| |
| Authors: | YE Lianhua LIU Xu LI Yunduo HUANG Songlei HUANG Zhangcheng |
| |
| Affiliation: | 1.State Key Laboratory of Transducer Technology, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China2.Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China3.University of Chinese Academy of Sciences, Beijing 100049, China |
| |
| Abstract: | In this paper, a high-speed data transmission model is presented for the digital signal output of a large-format high-frame-rate readout integrated circuit. We utilize the lumped parameter model to investigate the relationship between 3 dB bandwidth, response time, and device parameters. It is indicated that the size of the driver and the load of the transmission bus are the key parameters that determine the high-speed time-domain response characteristics. Furthermore, by using the distributed parameter model and Elmore delay model, the analytic expression for response time is deduced with more accurate values, and the optimal design of the output stage toward maximum bandwidth is obtained. Under the typical constraint condition of layout and power dissipation in a 64×64 array, simulation results show that the output 3 dB bandwidth of the transmission gate and composite logic gate can reach 293 MHz and 395 MHz, respectively. |
| |
| Keywords: | large-format high-frame-rate readout integrated circuit data transmission Elmore delay model |
| 本文献已被 维普 万方数据 等数据库收录！ |
| 点击此处可从《红外技术》浏览原始摘要信息 |
|
点击此处可从《红外技术》下载全文 |
|
