Crosstalk cancelling voltage‐mode driver for multi‐Gbps parallel DRAM interface |
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| Authors: | Younghoon Kim Changsik Yoo |
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| Affiliation: | Integrated Circuits Lab. Department of Electronic Engineering, Hanyang University, Seoul, Korea |
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| Abstract: | For multi‐Gb/s/pin parallel dynamic random access memory (DRAM) interface, a crosstalk cancelling voltage‐mode driver is proposed. The voltage‐mode driver is composed of a main driver and sub‐drivers where the cancellation signal is generated by the sub‐drivers. The outputs of the main driver and sub‐drivers are combined by a capacitive coupling so the direct current (DC) output swing is not affected by the crosstalk cancellation and the sub‐drivers may not consume DC power. The proposed crosstalk cancelling voltage‐mode driver implemented in a 0.11‐µm complementary metal‐oxide semiconductor (CMOS) technology improves the horizontal eye openings by 22.6 ps at 4‐Gbps/pin. Copyright © 2014 John Wiley & Sons, Ltd. |
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| Keywords: | crosstalk crosstalk induced jitter single‐ended signalling voltage‐mode driver DRAM CMOS |
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