| 低功耗并行的二维离散小波变换的VLSI结构 |
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| 引用本文： | 刘鸿瑾,何星,张铁军,王东辉,于其英,侯朝焕.低功耗并行的二维离散小波变换的VLSI结构[J].计算机工程与应用,2008,44(18):73-75. |
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| 作者姓名： | 刘鸿瑾 何星 张铁军 王东辉 于其英 侯朝焕 |
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| 作者单位： | 1.中国科学院 声学所，北京 100080 2.中国科学院 研究生院，北京 100039 3.山东省昌邑市奎聚中学，山东 昌邑 261300 |
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| 摘 要： | 提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理，不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块，该结构同时可以对两行数据进行处理，硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现，大大降低了需要的片上存储器的数量以及对片外存储器的访问，有效地降低了系统的功耗。
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| 关 键 词： | 离散小波变换 VLSI 提升算法 低功耗 并行 |
| 收稿时间： | 2007-9-18 |
| 修稿时间： | 2008-1-9
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Low power parallel VLSI architecture for 2-D discrete wavelet transform |
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| LIU Hong-jin,HE Xing,ZHANG Tie-jun,WANG Dong-hui,YU Qi-ying,HOU Chao-huan.Low power parallel VLSI architecture for 2-D discrete wavelet transform[J].Computer Engineering and Applications,2008,44(18):73-75. |
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| Authors: | LIU Hong-jin HE Xing ZHANG Tie-jun WANG Dong-hui YU Qi-ying HOU Chao-huan |
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| Affiliation: | 1.Institute of Acoustics，Chinese Academy of Sciences，Beijing 100080，China 2.Graduate University of Chinese Academy of Sciences，Beijing 100039，China 3.Kuiju High School of Shandong Province，Changyi，Shandong 261300，China |
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| Abstract: | A highly efficient VLSI architecture for the (9/7) 2-D DWT based on a lifting scheme is presented.The proposed architecture processes the row and column transforms simultaneously,eliminates the memory buffer for the column transform coefficients.The hardware utilization is speeded up to 100% by processing two independent data streams together using shared arithmetic functional blocks.And the embedded boundary extension circuit is exploited to optimize the architecture.Compared to previous architectures,the proposed architecture has more efficiency on critical path,power consumption,temporal storage usage and hardware utilization. |
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| Keywords: | Discrete Wavelet Transform(DWT) VLSI architecture lifting scheme low power parallel |
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