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嵌入式软硬件低功耗优化研究综述*
引用本文:周宽久,迟宗正,西方.嵌入式软硬件低功耗优化研究综述*[J].计算机应用研究,2010,27(2):423-428.
作者姓名:周宽久  迟宗正  西方
作者单位:大连理工大学,软件学院,辽宁,大连,116620
基金项目:大连市信息产业局IT专项基金资助项目(DL 2008 0243)
摘    要:随着时代的进步,制约着嵌入式设备广泛应用的障碍不再是处理器的速度、芯片的工艺,而是设备功耗。如何在相同能量的供给情况下工作时间最长、完成的任务最多,或者是运行相同的程序使用较少的能量成为嵌入式领域备受关注的研究方向。从硬件级、指令级和编译过程三个层次,由各层次相应公式的各个参数展开,对国内外的功耗优化研究现状进行综述和评价,并最终结合实验室SPARC仿真项目,提出基于SPARC仿真功耗优化研究的三个方向。

关 键 词:功耗优化    硬件级    指令级    编译优化    静态功耗    漏电流    内联优化    高速暂存区

Survey on power optimization of embedded software and hardware
ZHOU Kuan-jiu,CHI Zong-zheng,XI Fang.Survey on power optimization of embedded software and hardware[J].Application Research of Computers,2010,27(2):423-428.
Authors:ZHOU Kuan-jiu  CHI Zong-zheng  XI Fang
Affiliation:(School of Software Engineering, Dalian University of Technology & Science, Dalian Liaoning 116620, China)
Abstract:With the development of the embedded technology, wide applications of embedded technology will not be restricted by the speed of the processor and the design of the chip, but by the power consumption. How to accomplish more tasks with the same hardware resources attracts more and more attentions from the domestic and abroad scientists. This paper reviewed three research directions from hardware level, instructions level and compiling level. It proposed three future research directions based on the SPARC simulation project.
Keywords:power optimization  hardware level  instruction level  compilation optimization  static power consumption  leakage current  inline optimization  SPM(scratch pad memory)
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