Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

Experimental demonstration of wafer-scale growth of well-aligned, dense, single-walled carbon nanotubes on 4" ST-cut quartz wafers is presented. We developed a new carbon nanotube (CNT) wafer-scale growth process. This process allows quartz wafers to be heated to the CNT growth temperature of 865degC through the alpha-beta phase transformation temperature of quartz (573degC) without wafer fracture. We also demonstrate wafer-scale CNT transfer to transfer these aligned CNTs from quartz wafers to silicon wafers. The CNT transfer process preserves CNT density and alignment. Carbon nanotube FETs fabricated using these transferred CNTs exhibit high yield. Wafer-scale growth and wafer-scale transfer of aligned CNTs enable carbon nanotube very large-scale integration circuits and their large-scale integration with silicon CMOS.     

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20?μm down to 200?nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ～2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11)?g?cm(-2)?Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.     

转换阵列式碳纳米管薄膜至铝箔上的工艺

描述了一种将阵列式碳纳米管(CNTs)膜从石英基底转移至新基底(铝箔)上的工艺。用SEM检测了转移至铝箔上后各层膜的形貌并测试了铝箔CNTs膜的电阻。结果表明转基底工艺可以显著提高CNTs薄膜的利用率。去除90%不干胶后铝基CNTs薄膜的电阻可以达到0.3Ω以下。     

Flexible High‐Conductivity Carbon‐Nanotube Interconnects Made by Rolling and Printing

Applications of carbon nanotubes (CNTs) in flexible and complementary metal‐oxide‐semiconductor (CMOS)‐based electronic and energy devices are impeded due to typically low CNT areal densities, growth temperatures that are incompatible with device substrates, and challenges in large‐area alignment and interconnection. A scalable method for continuous fabrication and transfer printing of dense horizontally aligned CNT (HA‐CNT) ribbon interconnects is presented. The process combines vertically aligned CNT (VA‐CNT) growth by thermal chemical vapor deposition, a novel mechanical rolling process to transform the VA‐CNTs to HA‐CNTs, and adhesion‐controlled transfer printing without needing a carrier film. The rolling force determines the HA‐CNT packing fraction and the HA‐CNTs are processed by conventional lithography. An electrical resistivity of 2 mΩ · cm is measured for ribbons having 800‐nm thickness, while the resistivity of copper is 100 times lower, a value that exceeds most CNT assemblies made to date, and significant improvements can be made in CNT structural quality. This rolling and printing process could be scaled to full wafer areas and more complex architectures such as continuous CNT sheets and multidirectional patterns could be achieved by straightforward design of the CNT growth process and/or multiple rolling and printing sequences.     

On-chip deposition of carbon nanotubes using CMOS microhotplates

The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500?°C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g.?smart gas sensing) where the integration of CMOS and carbon nanotubes is required.     

金属栅回刻平坦化技术

随着CMOS集成电路技术节点缩减到45 nm及以下,高K金属栅(HK/MG)的后栅集成工艺已逐渐成为先进集成电路制造中的主流技术。其中金属栅(假栅)集成结构的平坦化是实现后栅集成的关键技术之一。本文通过特色开发的SOG两步等离子体回刻结合O2原位处理技术,克服了常规反应离子刻蚀中由于聚合物分布不均对刻蚀速度带来的不利影响,实现了隔离绝缘层低达4.19%(边缘去除5 mm)的片内非均匀性。不同稀疏与密集线阵列的亚微米CMOS后栅结构表明良好的平坦化效果并且避免了类似CMP(Chemical Mechanical Polish)工艺中常出现的"碟形效应"问题。所研制成功的无CMP后栅平坦化工艺为制备纳米级高K金属栅CMOS后栅器件打下了重要基础。     

Photolithographic fabrication of gated self-aligned parallel electron beam emitters with a single-stranded carbon nanotube

In this paper we report on the development of a photolithographic process to fabricate a gated-emitter array with single-stranded carbon nanotubes (CNTs) self-aligned to the center of the emitter gate using plasma-enhanced chemical vapor deposition (PECVD). Si tips are formed on a silicon wafer by anisotropic etching of Si using SiO(2) as a mask. Deposition of a SiO(2) insulating layer and Cr-W electrode layers creates protrusions above the Si tips. This wafer is polished, and the Cr-W on the tips is removed. Etching of the SiO(2) using hydrofluoric acid is performed to expose the gated Si tip. Incorporation of a novel diffusion process produces single-stranded CNTs by depositing a thin Ni layer on the Si tips and thermally diffusing the Ni layer to yield a catalyst particle for single-stranded CNT growth. The large surface to volume ratio at the apex of the Si tip allows a Ni particle to remain to act as a catalyst to grow a single-stranded CNT for fabricating the CNT based emitter structure. Diffusion of the Ni is carried out in situ during the heating phase of the PECVD CNT growth process at 600?°C. The diameters of the observed CNTs are on the order of 20?nm. The field emission characteristics of the gated field emitters are evaluated. The measured turn-on voltage of the gated emitter is 5?V.     

SEM and raman spectroscopy of multiwalled carbon nanotubes grown by novel technique of ash supported catalysts

Multiwalled carbon nanotubes (MWCNTs) were grown on a novel ASC catalyst and on catalyst deposited by SCC method on silicon wafer, by thermal CVD of acetylene. Fe and Ni were used as catalyst for ASC. Samples were analyzed by SEM and Raman spectroscopy. SEM analysis shows that CNTs grown on ASC have narrower diameter distribution (64+/-6 nm) compared to CNTs grown on SCC (67+/-10.5 nm). However, SEM and Raman spectroscopy studies show CNTs grown on SCC are of better quality. The same samples were studied after standard purification procedure of oxidation after annealing at high temperatures. SEM and Raman spectroscopy show that overall quality of ensemble of CNTs has improved. After annealing, diameter decreases for larger diameter approximately 200 nm nanotubes while it increases for CNTs of smaller diameter approximately 70 nm. To explain the increase in diameter of approximately 70 nm CNT's, a phenomenological model has been proposed. The results of Raman spectroscopy and SEM corroborate the proposed model.     

Ultra-Low-Powered Aqueous Shear Stress Sensors Based on Bulk EG-CNTs Integrated in Microfluidic Systems

Novel aqueous shear stress sensors based on bulk carbon nanotubes (CNTs) were developed by utilizing microelectricalmechanical system (MEMS) compatible fabrication technology. The sensors were fabricated on glass substrates by batch assembling electronics-grade CNTs (EG-CNTs) as sensing elements between microelectrode pairs using dielectrophoretic technique. Then, the CNT sensors were permanently integrated in glass–polydimethylsiloxane (PDMS) microfluidic channels by using standard glass–PDMS bonding process. Upon exposure to deionized (DI) water flow in the microchannel, the characteristics of the CNT sensors were investigated at room temperature under constant current (CC) mode. The specific electrical responses of the CNT sensors at different currents have been measured. It was found that the electrical resistance of the CNT sensors increased noticeably in response to the introduction of fluid shear stress when low activation current (≪1 mA) was used, and unexpectedly decreased when the current exceeded 5 mA. We have shown that the sensor could be activated using input currents as low as 100 $mu$A to measure the flow shear stress. The experimental results showed that the output resistance change could be plotted as a linear function of the shear stress to the one-third power. This result proved that the EG-CNT sensors can be operated as conventional thermal flow sensors but only require ultra-low activation power ($sim 1$ $mu$W), which is $sim 1000$ times lower than the conventional MEMS thermal flow sensors.      

Large-area, high-speed patterning of carbon nanotubes using material-assisted excimer laser photoablation

Large-area patterning of carbon nanotubes (CNTs) using a nonlithographic process is demonstrated. Projection imaging with deep ultraviolet radiation from 248 nm KrF excimer laser and material-assisted photoablation were used to pattern the CNTs. A matrix of CNTs dissolved in a DMF solution was deposited on a silicon wafer by spin coating, followed by coating of photodefinable polyimide on the CNTs. The CNTs and the polyimide layer were simultaneously patterned by the excimer laser projection photoablation process. Even though CNTs cannot be directly photoablated by low-fluence excimer laser radiation, simultaneous patterning of the illuminated CNT-polyimide combination region occurred due to the physical force of dissociated fragments of polyimide layer. We have demonstrated clean, large-area patterning of CNTs on 100 mm diameter Si wafers. Additionally, this patterning process is economical and provides higher throughput compared with conventional methods.     

Electronic sensitivity of a single-walled carbon nanotube to internal electrolyte composition

Carbon nanotubes (CNTs) are well known as materials for nanoelectronics and show great potential to be used as the sensing elements in chemical and biological sensors. Recently, CNTs have been shown to be effective nanofluidic channels and the transport of substances through small diameter CNTs is intrinsically fast, selective, and operates at the single molecule level. It has been shown that the transport characteristics of semiconducting single-walled CNT (SWCNT) field effect transistors (FETs) are sensitive to internal water wetting. We report here that the characteristics of semiconducting SWCNT FETs are also sensitive to the concentration, pH and ion type of the ionic solution when the electrolyte is inside the CNT. Such sensitivity is not observed at the outside surface of a semiconducting SWCNT. This opens a new avenue for building new types of CNT sensor devices in which the SWCNT concurrently functions as a nanochannel and an electronic detector.     

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related nonidealities and imperfections, and parasitic resistances and capacitances extracted from the CNFET circuit layout. We use Monte Carlo simulations using the CNFET SPICE model to investigate the effects of three major CNT process-related imperfections on circuit-level performance: 1) doping variations in the CNFET source and drain regions; 2) CNT diameter variations; and 3) variations caused by the removal of metallic CNTs. The simulation results indicate that metallic CNT removal has the most impact on CNFET variation; less than 8% of CNTs grown should be metallic to reduce circuit performance variation. This paper also presents an analytical model for the scalability of CNFET technology. High CNT density (250 CNTs/mum) is critical to ensure that performance (delay and energy) gains over silicon CMOS are maintained or improved with shrinking lithographic dimensions.     

Root growth of multi-wall carbon nanotubes by MPCVD

This work examines the relationships among the growth and interlayer reactions of carbon nanotubes (CNTs) to develop an effective process for controlling the nanostructure, orientation and characteristics of CNTs. Vertically oriented CNTs were successfully synthesized by microwave plasma chemical vapor deposition (MPCVD) with CH₄/H₂ as source gases. Additionally, the Ti and SiO₂ barrier layers and the Co catalyst were used in an experiment on the growth of CNTs on the Si wafer. Then, the SiO₂ barrier layer was deposited by low-pressure chemical vapor deposition (LPCVD). The Ti barrier layer and Co catalyst films were deposited on the Si wafer by physical vapor deposition (PVD). The deposited nanostructures were characterized by scanning and transmission electron microscopy, the results of which reveal that the deposited MWCNTs were grown under the influence of a catalyst on Si substrates with or without a barrier layer, by MPCVD. Vertically grown, dense MWCNTs attached to a catalytic film demonstrate that various MWCNTs penetrated the root particles. The diameter of the root particles, of approximately in the order of 100 nm, is larger than those of the tube, 10–15 nm. The well-known model of the growth of CNTs includes base- and tip-root growth. The interaction between the catalytic film and the supporting barrier layer is suggested to determine whether the catalytic particles are driven up or pinned down on the substrate during the growth.     

Wafer-level assembly of carbon nanotube networks using dielectrophoresis

We use dielectrophoresis (DEP) to controllably and simultaneously assemble multiple carbon nanotube (CNT) networks at the wafer level. By an appropriate choice of electrode dimensions and geometry, an electric field is generated that captures CNTs from a sizable volume of suspension, resulting in good CNT network uniformity and alignment. During the DEP process, the electrical characteristics of the CNT network are measured and correlated with the network morphology. These experiments give novel insight into the physics of DEP assembly of CNT networks, and demonstrate the scalability of DEP for future device applications.     

A CMOS Integrable Oscillator-Based Front End for High-Dynamic-Range Resistive Sensors

A new oscillating circuit is proposed to estimate the resistance and parallel parasitic capacitance of resistive chemical sensors. The circuit is able to reveal the resistance in a wide range (from tens of kiloohms to more than 100 $hbox{G}Omega$) due to the adopted resistance-to-time technique. In addition, the parallel capacitance (up to 50 pF) can be estimated. The circuit, which does not need any initial calibration, is very simple and compact and is suitable to be integrated with a standard CMOS technology to obtain a low-cost and low-power device for a sensor array interface. Different kinds of postlayout simulations concerning the CMOS integrated implementation have been conducted. Experimental results obtained using a discrete prototype board, both on passive components and on real sensors (metal–oxide sensors), have shown good linearity and reduced percentage error with respect to the theoretical expectations.      

Elaboration of single wall carbon nanotubes-based gas sensors: Evaluating the bundling effect on the sensor performance

In this article, carbon nanotube (CNT)-based sensors have been prepared using dispersion techniques. Sensors are obtained from a dispersion of CNTs using either chloroform as a solvent or sodium dodecylbenzene sulfonate as a surfactant. These sensors are prepared by drop-cast deposition of the solutions on interdigitated electrodes. The organic solvent processing leads to CNT layers where carbon nanotubes are obtained as larger bundles, whereas smaller bundles and individual tubes are predominantly formed in the surfactant processing. Under gas exposure (NO₂), both sensors respond to low gas concentrations; however, the sensing layers composed of larger bundles of CNTs present a slightly different behaviour (in terms of rapid stabilisation and sensitivity) compared to those made of individual CNTs.     

Design, Manufacturing, and Testing of Single-Carbon-Nanotube-Based Infrared Sensors

As a 1-D nanostructural material, carbon nanotube (CNT) has attracted lot of attention and has been used to build various nanoelectronic devices due to its unique electronic properties. In this paper, a reliable and efficient nanomanufacturing process was developed for building single-CNT-based nanodevices by depositing the CNTs on the substrate surface and then aligning them to bridge the electrode gap using the atomic force microscopy (AFM) based nanomanipulation. With this technology, single CNT-based IR sensors have been fabricated for investigating CNT's electronic and photonic properties. The fabrication of single-CNT-based IR sensors demonstrated the reliability and efficiency of the nanomanufacturing process. Experimental tests on single-multiwalled-CNT-based IR sensors have shown much larger photocurrent and quantum efficiency than other reported studies. It has also been shown that a high signal to dark current ratio can be accomplished by single-walled-CNT (SWNT) based IR sensors. Moreover, the testing of SWNT-bundle-based IR sensors verified that the performance of CNT bundle/film-based nanoelectronic devices was limited by the mixing of semiconducting CNTs and metallic CNTs, as well as the unstable CNT–CNT junctions in a CNT bundle or network.      

The Future of Microelectromechanical systems (MEMS)

Abstract:  MEMS-based products produced in 2005 had a value of $8bn, 40% of which was sensors. The balance was for products that included micromachined features, such as ink jet print heads, catheters and RF IC chips with embedded inductors. Growth projections follow a hockey stick curve, with the value of products rising to $40bn in 2015 and $200bn in 2025! Growth to date has come from a combination of technology displacement, as exemplified by automotive pressure sensors and airbag accelerometers and new products, such as miniaturised guidance systems for military applications and wireless tire pressure sensors. Much of the growth in MEMS business is expected to come from products that are in the early stages of development or yet to be invented. Some of these devices include disposable chips for performing assays on blood and tissue samples, which are now performed in hospital laboratories, integrated optical switching and processing chips, and various RF communication and remote sensing products.The key to enabling the projected 25-fold growth in MEMS products is development of appropriate technologies for integrating multiple devices with electronics on a single chip. At present, there are two approaches to integrating MEMS devices with electronics. Either the MEMS device is fabricated in polysilicon, as part of the CMOS wafer fabrication sequence or a discrete MEMS device is packaged with a separate ASIC chip. Neither of these approaches is entirely satisfactory, though, for building the high-value, system-on-chip products that are envisioned. It is this author's opinion that a combination of self-assembly techniques in conjunction with wafer stacking, offer a viable path to realizing ubiquitous, complex MEMS systems.     

CMOS 图像传感器的发展现状

目的　了解当前 CMOS图像传感器的发展状况 .方法　详细介绍了图像传感器的历史背景、发展现状、像素单元的结构、工作原理以及 CMOS图像传感器芯片的整体结构 ,并比较了 CMOS图像传感器和 CCD图像传感器的优、缺点 .结果　指出了 CMOS图像传感器发展趋势 .结论　 CMOS图像传感器具有美好的发展前途