Low-voltage dynamic BiCMOS CLA circuit with carry skip using novelfull-swing logic

This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies     

Gallium arsenide pseudo-dynamic latched logic

A new GaAs logic family, pseudo-dynamic latched logic (PDLL). is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems     

Design and performance of multistage GaAs dynamic logic

GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

GaAs capacitively coupled domino logic gate

A novel GaAs capacitively coupled domino logic (CCDL) gate is proposed. Derived from capacitor-coupled logic, this domino gate offers complex gate design capability with relatively low power dissipation and high speed, making it suitable for VLSI implementations.<>     

Gallium arsenide finds a new niche

The use of a very-large-scale integrated GaAs circuits for applications where high speed at room temperatures is needed, such as in computers or telecommunications, is examined. The advantages and disadvantages of a logic family called direct-coupled FET logic (DCFL) which couples the speed of GaAs with a significantly lower power dissipation than any other alternative are discussed. Material, fabrication, and packaging concerns associated with DCFL are considered. Some GaAs devices being produced in volume, at rates of several hundred a month, are described. The potential impact of these devices on the computer and telecommunications markets is addressed     

Efficient design of gallium arsenide Muller-C element

A Muller-C element is a fundamental building block of a handshake path in self-timed digital circuits. It is a basic event driven logic (EDL) gate, implementing the AND function for events. The authors present a new, improved design of the Muller-C element using GaAs MESFET technology. A static Muller-C gate is implemented that incorporates modifications of newly introduced, GaAs pseudodynamic latched logic family (PDLL) primitives. The circuit is characterised by very high speed and low power dissipation     

Analysis of GaAs FET's for integrated logic

This paper presents an analysis of the speed and power dissipation of various GaAs FET inverter circuits as prototypes of integrated logic circuit design. The analysis provides analytical expressions to assess the switching performance of enhancement-mode and depletion-mode MESFET's and JFET's with respect to switching-speed and power-dissipation capabilities in optimized configurations. Various load elements are described and analyzed for circuit applications. The various logic gates, now under development, are compared in their switching performance and a review of the state of the art is given. Prospects of large-scale integration (LSI) of gigabit logic for GaAs FET's are assessed.     

Selectively doped heterostructure frequency dividers

The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having 1-µm gate lengths and 4-µm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al.3Ga.7As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.     

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1-μm GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW     

An 11-GHz GaAs frequency divider using source-coupled FET Logic

A GaAs one-fourth frequency divider is fabricated to evaluate the ultrahigh-speed performance of source-coupled FET logic (SCFL) having normally-on FET's with small negative V th values. High-transconductance (240 ms/mm) 1/2-µm gate-length FET's and an air-bridge interconnection line technology are successfully developed. A maximum toggle frequency Fmaxof 11 GHz is achieved with a power dissipation of 149 mW. Furthermore, 9.7-GHz Fmaxwith low power dissipation of 52 mW was also obtained.     

超前进位加法器混合模块延迟公式及优化序列

为扩展操作位数提出了一种更具普遍性的长加法器结构——混合模块级联超前进位加法器。在超前进位加法器(CLA)单元电路优化和门电路标准延迟模型的基础上，由进位关键路径推导出混合模块级联CLA的模块延迟时间公式，阐明了公式中各项的意义。作为特例，自然地导出了相同模块级联CLA的模块延迟时间公式。并得出和证明了按模块层数递增级联序列是混合模块级联CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列。这一结论成为优化设计的一个设计规则。还给出了级联序列数的公式和应用实例。     

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.     

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon     

Propagation delay optimisation in multistage GaAs m.e.s.f.e.t. combinational logic circuits by use of dynamic programming

Propagation delays in multistage combinational logic circuits using GaAs metal-semiconductor field-effect transistors (m.e.s.f.e.t.s) are optimised subject to constraints on the overall power dissipation. Specific optimisation criteria are derived for 1-stage, 2-stage, and 3-stage combinational logic circuits. The results are evaluated with parameters of an existing process.     

Capacitor-coupled logic using GaAs depletion-mode f.e.t.s

A new method of interconnecting depletion-mode GaAs f.e.t. logic stages, using capacitive coupling, eliminates the need for a negative power supply and is more tolerant of processing spreads, particularly of pinch-off voltage. The technique may be combined with conventional level shifting, operating at very low current. The use of capacitance may be extended to achieve clocked dynamic data storage with very low power dissipation.     

An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.     

GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟约１００ｐｓ、单门功耗约１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型ＤＣＦＬ电路，且Ｅ／Ｅ型电路较Ｅ／Ｄ型电路具有更高的成品率。     

A 2.5-ns, 40-mW, 4/spl times/4 GaAs multiplier in two's complement mode

The design, fabrication, and testing of a very fast GaAs 4/spl times/4 parallel multiplier based on the modified Booth's algorithm are described. The multiplier includes novel transfer logic cells and is the first high-performance GaAs two's-complement multiplier. The circuit, fabricated with 1-/spl mu/m aligned process, exhibits a multiplication time of 2.5 ns (typical 2.7 ns) on the critical path, with a 40-mW power consumption. Per gate the average delay is 120 ps, at 0.2-mW dissipation.