Ferroelectric phase shifters and their performance in microwave phased array antennas

Abstract

Recent advances in the development of Barium Strontium Titanate ferroelectric composition has made possible reasonable performance of ferroeletric phase shifters to frequencies up to 10 GHz. These material improvements, coupled with phase shifter circuit design changes have resulted in phase shifts greater than 360 degrees with less than 6 dB insertion loss. In particular additives to the BaxSr1-_xTiO₃ composition have been shown to exhibit a consistent electrical phase shift verses DC potential over parameters of temperature and humidity. These ferroelectric material improvements and circuit design changes, included with the development of multiple ferroelectric phase shifters makes possible the fabrication of a low cost electronic scanning antenna. A single four element phase shifter was used with a one dimensional linear antenna array which was constructed on three layers and used an aperture coupled distribution technique. Individual elements of this multiple four element phase shifter were evaluated with respect to uniformity phase shift and insertion loss. The four element antenna was fed by four ferroelectric phase shifters and the phase shifters are corporately fed by the microwave source. The ferroelectric phase shifters are controlled via a dedicated microcontroller which calibrates out element phase variations and provides a real time scan capability for the antenna assembly.     

360°低插损小型化反射式移相器设计

针对第5代移动通信大规模多输入多输出(massive MIMO)和无线回传系统中移相阵列的应用需求,本文对反射式移相器(RTPS)的模型拓扑进行了对比分析,提出了四元件双可调(FEDA)负载拓扑的设计方法和相位变换的调整方式,研究了移相步进和插入损耗的影响因素,采用数字变容管(DTC)进行RTPS的调谐设计。实验结果表明,在4.4～5.0 GHz全频段范围内实测移相范围大于360°,移相步进小于12°,插入损耗小于1.8 dB,尺寸仅为10 mm×8 mm,兼具低插损、小型化、大带宽、高精度、易控制等优点。     

Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

This paper reports the analyses of the inductive degeneration , noise filter , and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. Copyright © 2017 John Wiley & Sons, Ltd.     

A variable structure static phase shifting transformer for power system stabilization

A variable structure sliding mode control system for controlling a static phase shifter is developed. The static phase shifter aims at introducing voltage phase shift between the terminals of transmission line. The voltage phase shift is controlled by adding to the voltage of one end of transmission line a quadrature voltage component. The thyristor switches is used to regulate that quadrature component, whereupon, the phase shift is changed. A sample power system model used for digital simulation is linearzied to design the variable structure control algorithm. To validate the power and robustness of the proposed controller for enhancing power system stability, the studied power system is subjected to different disturbances such as tie line power, frequency or synchronous machine speed disturbances. The power system dynamic responses for the above disturbances prove the effectiveness and superiority of the variable structure control system in terms of fast damping response with less settling time.     

Optimum Reflection-Type Phase Shifter Using (Ba,Sr)TiO3 Thin Film

In this paper, in order to obtain a large differential phase shift with a little change in applied voltage, a ferroelectric reflective load circuit has been designed on top of barium strontium titanate (Ba,Sr)TiO₃ [BST] thin film. The design of the ferroelectric reflection-type phase shifter is based on a reflection theory of terminating circuit, which has a reflection-type analogue phase shifter with two ports terminated in symmetric phase-controllable reflective networks. To achieve large amounts of phase shift in low bias-voltage range, the effects of change of capacitance and transmission line connected with two coupled ports of a 3-dB 90° branch-line hybrid coupler have been investigated. A large phase shift with a small capacitance change in the parallel terminating circuit has been demonstrated in the paper.     

Low-loss 7-bit S-band CMOS passive phase shifter with digital control

This paper presents the design and implementation of a 7-bit S-band digital passive phase shifter using Complementary Metal-Oxide-Semiconductor (CMOS) 65-nm technology in 2.6- to 3.2-GHz frequency band. New switched delay network topology has been used for 5.625° and 2.8°, and modified switched filter topology has been used for implementation of other phase bits to achieve 7-bit performance with low insertion loss and better isolation. The measured results of the fabricated chip show 7-bit performance with an average insertion loss of 11 dB, average root mean square (RMS) phase error of less than 2.0°, average RMS amplitude error of less than 0.6 dB, input matching (S₁₁) better than −7.5 dB, and output matching (S₂₂) better than −14.5 dB across the target frequency band at 50Ω input/output impedance.     

Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band

This paper presents a design of a CMOS cross-coupled voltage-controlled oscillator (VCO) using active inductors (AIs) for wide-band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator-C topology as the basic structure to generate an inductance. The VCO uses a cross-coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65-nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1-MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm² including the pads. The proposed AI-VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.     

Compact Distributed Phase Shifters at X-Band Using BST

A new type of distributed analog phase shifter is presented that utilizes the coplanar strip transmission line topology. This transmission line has several benefits for phase shifter design, resulting in decreased physical dimensions and potentially lower losses. A prototype was constructed using thin-film barium strontium titante (BST) varactor technology. The design achieved a 49°/dB figure of merit at 10 GHz. The performance and chip area of the coplanar strip circuit are compared with designs using coplanar waveguide and synthetic lumped element transmission lines.     

一种用于相移干涉仪的高压放大电路

基于自主研制高精度数字化相移干涉仪的需求,针对干涉仪的压电陶瓷移相器设计了一种高压放大电路。通过双极性运算放大器OP07构成低噪声,非斩波稳零的低压放大电路与中功率线性三极管MJE340和MJE350构成高压放大电路进行直流耦合,结合反馈网络,功率放大电路,滤波电路以及限流保护电路,将计算机输出的0~5 V低电压的移相控制信号稳定线性放大到-30 V~+130 V范围,且输出低至10 mV 峰值的纹波,满足压电陶瓷移相器的高压驱动控制要求和相移干涉仪的高精度移相测量的要求。     

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal‐oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28‐nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1‐MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd.     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.     

A low-loss compact six-bit DMTL phase shifter for phased array antenna applications

A phase shifter is one of the main components of radars and phased array systems. In this paper, a novel three-state two-bridge unit cell is presented for a compact low-loss six-bit distributed microelectromechanical systems (MEMS) transmission line (DMTL) phase shifter. The proposed unit cell includes a coplanar waveguide (CPW) transmission line, a MEMS bridge on the signal line, two metal-air-metal (MAM) capacitors on a glass substrate, and two additional electrodes under the MEMS bridge, near the signal line. Using these electrodes, it is possible to generate two different phase states employing the MEMS bridge, and the third state is produced by a metal-air-metal (MAM) bridge. Hence, the designed structure can generate three different phase shifts per unit cell (i.e., 5.625°, 11.25°, and 22.5° phase shifts). The novelty of this design is that the number of unit cells is considerably reduced from 64 in a conventional six-bit phase shifter to only 17 in our design. Therefore, the total length of the six-bit phase shifter and average loss are considerably reduced. The designed structure is calculated and simulated at 32 GHz using MATLAB and ANSOFT HFSS, respectively. According to the calculation and simulation results, the lateral size of the phase shifter is only 8.5 mm, the root mean square (RMS) phase error is 1.38°, and the average loss is 1.1 dB. The feasibility of the proposed design is investigated using the proposed fabrication process. The designed phase shifter can be easily scaled to other frequencies for radar and satellite applications with more bits.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

Evaluating voltage-tunable materials for RF phase shifter technology

Abstract

Today's phased-array antennas use hundreds of radiating elements that use relatively high-loss phase shifters that operate over a limited bandwidth. The number of elements and the phase shifter losses affect the overall cost of the antenna system. Ferroelectric RF phase shifters have the potential to meet the low-loss, low-cost requirements driving many phased-array applications. Some of the issues affecting the development of ferroelectric phase shifters include ferroelectric tunability, dielectric losses, conductor losses, and impedance mismatch. We used the measured tunability (250 kHz, room temperature), dielectric constant, and loss tangent (10 GHz, room temperature) of Ba_1-xSr_x/TiO₃ (0.4x 0.6) with various amounts of MgO additive, 0 to 60 wt.%, to estimate the device performance of microstrip phase shifters. The electromagnetic model of the microstrip (which uses a standard 3-mil-wide 1-oz. copper line, 3-mil-thick BST/MgO composite and the bias criteria of 2 V/μm) has produced performance benchmarks for a number of composites providing 360° of phase shift. While the accuracy of the electromagnetic model used to evaluate these materials has limitations, the results do provide some insight as to which materials may be better suited for 10-GHz phase shift devices.     

A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

移相器自动测试系统

移相器是相控阵雷达中用于实现波束移相功能的基本电路.本文描述移相器自动测试系统的原理和组成,着重介绍了测试夹具、控制电路、驱动和测试软件设计等关键技术.经过实际应用证明,该测试系统通用性好,自动化程度高,很容易实现移相器的自动测试需求,为移相器的研制和验收提供了极好的测试手段.     

Reflection-Type Ferroelectric Phase Shifter With Defected Ground Structure

In order to obtain a low-loss ferroelectric phase shifter, we were designed and fabricated the reflection-type ferroelectric phase shifter with the defected ground structure (DGS) resonators. The ferroelectric phase shifter is consisted of a 3-dB 90° branch-line hybrid coupler and terminated reflective circuit with tunable ferroelectric DGS resonator which can provide a high Q resonator characteristic at high frequencies. The design parameters of equivalent circuit for the tunable DGS resonator are derived by circuit analysis method and three-dimensional full wave finite element method. At 13.5 GHz, the fabricated phase shifter exhibited an insertion loss of better than 3.4 dB.     

Millimeter-Wave Loaded Line Ferroelectric Phase Shifters

Ferroelectric loaded line phase shifters operating at millimeter waves for phased array antenna applications are presented. Phase shifters were manufactured on using Ba_0.3Sr_0.7TiO₃ thin films. The magnetron sputtering process was used to fabricate these Ba_0.3Sr_0.7TiO₃ ferroelectric films with a thickness ～1 μm. The phase shifter operating at V-band (60 GHz) demonstrated continuous phase shift up to 220 deg and figure of merit (FOM) 22 deg/dB. The phase shifter operating at Ka-band (30 GHz) showed phase shift up to 360 deg and FOM 40 deg/dB.