基于软件无线电的导航信号直接带通采样方案研究

航电系统中,软件无线电被认为是实现射频综合的最佳途径。研究了导航信号的射频直接采样方法,对双频段的直接带通采样进行了分析,给出了双频段有效采样频率的计算方法。针对我国北斗卫星1．2GHz和1．5GHz2个频点附近的导航信号,按照文中给出的直接带通采样频率的计算方法确定了有效的采样频率,并进行了相应的Matlab仿真实验...     

基于GNU Radio和USRP2的未知信号检测

运用开源软件无线电(GNU's Not Unix Radio,GNU Radio)技术和与之配套的通用软件无线电外设(TheSecond-generation Universal Software Radio Peripheral,USRP2),设计出了未知无线电信号自动检测系统。系统采用能量检测法,能够快速识别一定频段内未知无线电信号,并记录其带宽、中心频率和起止时间,同时存储相应的同相正交(Inphaseand Quadrature,IQ)数据,为后续载频的精确估计提供必要的参数。在实际测试中发现,该系统检测速度快、准确率高,对未知强信号检测具有一定的可靠性和实用性。     

软件无线电中的带通采样分析

近年来,软件无线电技术以其强大的通用性和灵活性得到了广泛发展和应用。研究了软件无线电中广泛采用的带通采样技术。在给出带通采样定理一般结论的基础上,重点分析了实现无混叠带通采样的条件,得到了边界频率点上4种不同取值情况下带通采样频率的取值范围,并利用时域内插进行了带通采样信号的完全重建。最后,采用Matlab进行了仿真验证。     

软件无线电中A/D孔径抖动研究与仿真

在软件无线电A/D处理信号频率较高的情况下,采样时钟误差即孔径抖动对信噪比的影响不可忽略,提出了一种孔径抖动对软件无线电系统信噪比影响的数学分析方法。同时以单音和WCDMA中频信号A/D系统为例,通过仿真验证了分析结论。     

RAQ’S非常见问题解答 来自ADI公司的电话记录中奇怪但真实的故事

过采样和欠采样问:为什么很多现代ADC的信号带宽要远远大于其最大采样频率?根据采样理论,信号频率不是应该限制为采样频率的一半吗?还有,输入级带宽较小不是可以降低功耗吗?     

大动态信号处理中的高速数字采样

本文概述了抗干扰天线的基本原理。根据信号频率、带宽选用合适的采样定理计算出采样频率。根据要处理的信号中的有用信号、噪声、干扰幅值之间的关系确定AD器件的采样精度为14位。采样时钟信号采用差分输入,从而降低了时钟信号的相位噪声减少码间干扰。根据数字信号的特点选择合适的存储方式。     

无线电系统工程EMC设计中的频率因素

频率是表征无线电信号的主要特征之一,是 EMC(电磁兼容性)设计和 EMI(电磁干扰)分析的关健因素。无线电频谱是有限的自然资源,合理、有效地使用无线电频谱已成为无线电系统工程中的重要课题。本文论述了无线电系统工程中有关频段选择与频率分配、干扰类型、带宽限制、频率容差、频率间隔、杂散发射与杂散响应、频谱管理等内容,可供从事无线电系统设计和 EMC 分析的同志参考。     

带通采样在数字多通道中频接收机中的应用

论述了带通信号采样定理,在对带通采样后的频谱结构做了详细分析的基础上,提出中频频率、采样频率的选取方法。将带通欠采样技术运用到软件无线电中频接收机设计中,并给出了带通采样定理在的不同条件下Matlab仿真的结果,验证了带通采样技术在宽带数字多通道、多速率、多模式软件无线电中频接收机设计中的可行性和实用性,在工程应用中具有较大的参考意义。     

一种VWDK调制的边带抑制方法及VWDK性能研究

传输带宽对信号传输的带宽效率有着重要的意义.本文讨论了一种较大幅度抑制VWDK调制传输带宽的滤波方法.首先通过设计和使用VWDK整形滤波器大幅度压缩了VWDK已调信号传输带宽;其次接收端使用逆滤波大幅降低了采样频率;最后在逆滤波后选择、使用带通滤波器进一步降低了满足一定解调要求的信噪比.     

基于多通道重构的DPCA SAR方位向信号处理

研究了一种基于方位向相位中心偏移天线技术的机载合成孔径雷达(SAR)实现方法。通过在方位向上安置相位中心偏移的多个波束来降低系统对脉冲重复频率的要求,从而在保证方位向分辨率不变的条件下能够扩展机载SAR的测绘带宽。针对由脉冲重复频率的变化造成的方位信号非均匀采样,采用了多通道重构算法来恢复均匀采样信号,以两通道机载SAR为例,通过仿真实例验证了该算法的有效性。     

孔径抖动对中频采样系统信噪比影响的研究

孔径抖动对中频(或射频)带通采样系统信噪比的影响非常严重.理论上,尽管相同带宽的中频信号和基带信号可以用相同的频率进行采样,但中频采样受孔径抖动等因素的影响更大,其采样技术要求也更高.如果在中频采样系统中解决不好孔径抖动问题,很可能根本采集不到正确的信号.本文通过分析孔径抖动产生的原因,孔径抖动与ADC (模数转换器)的信噪比以及与被采样信号上限频率之间的关系,找出了由孔径抖动决定的被采样信号的上限频率与ADC模拟带宽之间存在差距的原因,并发现了过采样率与处理增益及孔径抖动之间的关系.最后,介绍了几项减小孔径抖动的具体措施.     

中频带宽对调频遥测非相干解调性能影响分析

遥测地面站设备多采用非相干鉴频解调,设备接收机需要根据码速率来设置中频带宽,中频带宽设置不合理会导致遥测解调误码率增高。为在国军标规定的档数中选出不同码速率的相应最佳中频带宽,文中根据FM信号的解调原理,对非相干鉴频解调方式下,中频带宽对解调误码率性能的影响进行了仿真分析,依据仿真结果提出了最优误码性能下中频带宽参数的推荐值为1.7倍码速率,最后通过硬件实验对仿真分析结果进行了验证。     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

强干扰情况下用于CDMA系统的时空域联合处理

本文提出了一个时空域联合处理技术来对抗码分多址通信系统中的多址干扰.它由智能天线和多用户联合检测结合而成,智能天线可以压制与有用信号来向不同的干扰,余下的与用户信号来向相同的干扰可以被多用户联合检测系统消除.这种结构在干扰严重的信道仍能得到令人满意的效果.     

2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3

The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

A charge-domain quadrature sampling circuit realization in 0.35 /spl mu/m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply.     

宽带雷达中频直接采样与高速存储系统设计与实现

该文针对大瞬时带宽的宽带雷达回波信号中频直接采样需要解决的采样速率和高速海量数据实时连续存储等问题,首先根据带通信号无混叠采样条件确定了系统的采样速率,并依此提出了数字正交解调、缓存与高速实时无丢失存储等方案并进行了设计与实现。研制的中频信号高速采集实时存储系统基于机架服务器平台,采用QDRII SRAM 作为缓存,以PCIe 接口为数据传输通道。系统在某相控阵雷达实验平台中得到应用,通过外场实测,性能良好,为宽带雷达回波中频直接采集提供一种可行的实现方法。      

一种宽带信号数字下变频的实现方法

在宽带、超宽带应用中,单一信号带宽达几百兆赫兹;或者在不同中频同时调制多个信号产生的宽带信号也达数百兆赫兹,用常规的数字下变频方法很难实现。文章提出了一种基于DFT滤波器组的高效数字下变频结构,分析了该解调算法的特点和实现性能。对已知信号带宽和中频的宽带信号,对比了DFT滤波器组和多相分解算法的性能。对信号带宽和中频均在变化的信号,给出了实现思路。最后,给出了该DFT滤波器组的硬件实现方案。     

A 20 GHz microwave sampler

A microwave sampler circuit which operates over the frequency band of 1-20 GHz and has a number of novel features is described. These features include a wideband microstrip-to-slot balun and a wideband active isolator the function of which is to reduce the local oscillator to RF leakage from the input port of the sampler. The signal-to-noise ratio over the input bandwidth is greater than 20 dB at an input power level of -32 dBm. This signal-to-noise ratio was measured in an IF bandwidth of 175 MHz and includes the contribution from the IF amplifier. The sampler, which is made on alumina using MIC techniques, has an integrated impulse generator driven with a sinusoidal local oscillator of only 20 dBm over the frequency band of 250-350 MHz. The IF signal is in the 10-175-MHz band. The RF input VSWR is better than 2:1 up to 20 GHz, and the oscillator to RF breakthrough is better than -58 dBm (-78 dBc) when driven with a local oscillator of 20 dBm. This unusually low leakage was achieved by using the active isolator prior to the sampling circuit