A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

混合域实现图像块矩阵变换的CIS像素读出噪声分析

为了研究双存储像素的读出噪声对混合域实现图像块矩阵变换的CMOS图像传感器(CIS)产生的误差影响,对其进行噪声分析。结合双存储像素的工作时序,对实现图像块矩阵变换过程中由于多次采样和双路存储而增加的kTC噪声、源跟随器的1/f噪声和热噪声进行分析并建立数学模型,总结出双存储像素读出噪声对一次块矩阵变换的误差影响。以二维离散余弦变换为例,通过CHRT 0.35 m标准CMOS工艺电路仿真并结合matlab/simulink对比验证,得出增大存储电容、减小源跟随器宽长比可以降低由于像素读出噪声引起的误差。结果证明,此方法可以有效降低噪声,指导电路设计。     

General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

Single-chip image sensors with a digital processor array

The architectures, implementation and applications of two smart sensors, LAPP and PASIC, are described. The basic idea of these two designs is to integrate an image sensor array with a digital processor array in a single chip. The integrated camera-and-processor eliminates the bottleneck of sequential image read-out that characterizes conventional systems. They provide fast, compact and economic solutions for tasks such as industrial inspection, optical character recognition and robot vision.     

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

晕苯增强CMOS图像传感器

由于紫外光在硅中的穿透深度有限,以及多晶硅栅极对紫外光的吸收,导致传统的硅基CMOS图像传感器在紫外光波段的响应不高。在此,本文选择一种低成本的下转换法来提升CMOS图像传感器的紫外响应能力,采用真空热蒸发法分别在石英衬底和CMOS图像传感器的像敏面上蒸镀了晕苯薄膜,并对薄膜的光学性能、红外光谱、光稳定性和热稳定性进行了研究。实验结果表明,晕苯薄膜能吸收紫外光并发射出500 nm的绿色荧光,可以与CMOS图像传感器的光谱响应峰值很好地匹配;同时,发现晕苯红外吸收光谱的实验值和计算值基本吻合;薄膜在200 ℃温度下退火20 min后,其发射峰的荧光强度保持在原来的95.7%;在280 nm激发波长照射大约60 min后,发光强度呈指数衰减至初始值的64%。采用CMOS单色相机在可见光（400~780 nm）和紫外光（365 nm）下定性分析了薄膜的紫外增强效果,发现蒸镀晕苯薄膜后的CMOS单色相机可以提高对紫外光的灵敏度。     

Smart CMOS image sensor arrays

In this paper, we present several smart image sensor arrays intended for various applications. We discuss the realization of image sensors in CMOS technology and show some examples of one-dimensional (1-D) and two-dimensional (2-D) smart image arrays     

基于FPGA的CMOS线阵图像传感器数据采集系统设计

针对日本滨松公司的CMOS线阵图像传感器G9214-512S,设计基于FPGA的同步工作模式的图像数据采集系统,使用VHDL语言对此系统进行描述,并用Xilinx ISE Design Suit自带的ISim软件对设计的时序进行仿真。采用Xilinx公司的Spartan 3 XC3S200A-4VQ100进行FPGA配置和验证,仿真结果表明该数据采集系统的时序正确,具有较高的实用价值。     

A multispectral image sensor array

A silicon monolithic multispectral photosensor device is described. Fabrication techniques and preliminary spectral response data are presented.     

Motion estimation processor using mixed-signal approach

This paper describes the design, realization, and evaluation of a mixed-signal motion estimation processor using the full-search block-matching algorithm. The approach features digital I/O and a low-power, compact analog computational core. The proof-of-concept realization whose architecture incorporates pixel reuse, was fabricated in 0.8-/spl mu/m CMOS technology occupying 0.65 mm/sup 2/, and operates on 4 /spl times/ 4 pixel blocks and a search area of 8 /spl times/ 8 pixels. The processor achieves a low energy consumption per motion vector of 1.35 nJ and dissipates 0.8 mW from a 3-V power supply at QCIF 15 frames/s. The approach is intended for portable applications of digital video encoding.     

CMOS图像传感器的辐射实验

为了考察商用CMOS图像传感器应用于空间的可行性,对进行了空间辐射环境模拟实验研究.实验采用60Co-γ辐射源模拟空间辐射环境,辐射最大剂量为5× 104 rad(Si),辐射速率为1 Gy/s.在辐照时,根据实验需要在CMOS两端加偏置电压或不加偏置电压,并采用在线和离线测量相结合的方法.实验结果表明:辐射初期各项性...     

CMOS图像传感器新技术——C^3D

C3D(CMOS Color Captive Device)是新一代半导体成像技术,它不仅提高了像素设计技术,也改进了生产工艺.采用这种技术生产的0.25 μ mCMOS图像传感器能够在不牺牲性能的前提下增加晶体管的数量和占空因数(Fill Factor).除了增加像素设计的选择方案之外,还可实现更为复杂的功能和更低的功耗,并且在速度方面也很有优势.     

CMOS图像传感器及其研究

介绍了CMOS图像传感器的工作原理,比较了CCD图像传感器与CMOS图像传感器的优缺点,指出了CMOS图像传感器的技术问题和解决途径,综述了CMOS图像传感器的现状和发展趋势.     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

具有视网膜仿生处理功能的CMOS图像传感器

借鉴生物视网膜进行图像采集和处理的结构及功能,设计了具有视网膜仿生片上信号处理电路的智能CMOS图像传感器(CIS)。像元内的仿生处理电路主要由自适应光接受器、滤波网络和减法运算电路3部分构成;CIS采用结构简单的空间滤波电阻网络和基于运算放大器的减法电路分别模拟水平细胞和双极细胞的功能,实现图像的边缘检测。在Chartered 0.35μm 2P4M CMOS工艺参数下,对各单元电路及6×6 CIS阵列进行仿真。     

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.     

A CMOS image sensor with a double-junction active pixel

A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters.     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Real-time image template matching based on systolic array processor

An architecture based on a systolic array for real-time image template matching is presented. The architecture consists mainly of four elements: a digitizer, a two-dimensional systolic array combined with variable-length shift register arrays, an adder tree, and a comparator. All the elements form a four-stage pipeline. The image data enter the pipe sequentially in the same order as the TV raster scan. The matching computation is, however, performed in a parallel manner. The analyses on time complexity and hardware complexity have shown that real-time performance is achieved. The analyses have also shown that the processing speed is higher and the hardware is simpler when compared to the architecture presented by Chou and Chen.     

An array processor for general purpose digital image compression

A new VLSI processor (DIP chip) for image compression is presented which combines principles of multipipeline and array processing. The device is not specific to any one image compression algorithm and can be regarded as a general purpose processor. The chip has been implemented using a CMOS 1.0-μm process on a 14.4×13.5-mm² die. An internal clock frequency of 40 MHz results in 1.2×10⁹ operations/s on 8-bit data. Solutions to problems associated with the large bandwidth required, for both image data and instruction streams, is the main aim of the paper. The necessary problem of increasing the array clock frequency relative to the input/output clock frequency without the need for a large on-chip instruction cache or fast external clock speeds is also addressed