Investigation of impact ionization in thin GaAs diodes

The electron and hole multiplication coefficients, M_e and M_h, respectively, have been measured in thin GaAs homojunction PIN and NIP diodes and from conventional ionization analysis the effective electron and hole ionization coefficients, α and β, respectively, have been determined. The nominal intrinsic region thickness w of these structures ranges from 1.0 μm down to 25 nm. In the thicker structures, bulk-like behavior is observed; however, in the thinner structures, significant differences are found. As the i-regions become thinner and the electric fields increase, the M_e/M_h ratio is seen to approach unity. The experimental results are modeled and interpreted using a semianalytical solution of the Boltzmann equation. In thin (w⩽0.1 μm) devices the dead space effect reduces effective ionization coefficients below their bulk values at low values of carrier multiplication. However, overshoot effects compensate for this at extremely high fields (⩾1×10³ kV/cm)     

Avalanche multiplication characteristics ofAl0.8Ga0.2As diodes

The avalanche multiplication characteristics of Al_0.8Ga _0.2As have been investigated in a series of p-i-n and n-i-p diodes with i-region widths, w, varying from 1 μm to 0.025 μm. The electron ionization coefficient, α, is found to be consistently higher than the hole ionization coefficient, β, over the entire range of electric fields investigated. By contrast with Al_xGa _1-xAs (x⩽0.6) a significant difference between the electron and hole initiated multiplication characteristics of very thin Al_0.8Ga_0.2As diodes (w=0.025 μm) was observed. Dead space effects in the diodes with w⩽0.1 μm were found to reduce the multiplication at low bias below the values predicted from bulk ionization coefficients. Effective α and β that are independent of w have been deduced from measurements and are able to reproduce accurately the multiplication characteristics of diodes with w⩾0.1 μm and breakdown voltages of all diodes with good accuracy. By performing a simple correction for the dead space, the multiplication characteristics of even thinner diodes were also predicted with reasonable accuracy     

A simple model for avalanche multiplication including deadspaceeffects

A simple Monte Carlo model (SMC) using single effective parabolic valleys and accurately accounting for deadspace effects is presented for calculating the avalanche process. Very good agreement is achieved with a range of measured electron and hole multiplication results from GaAs p ⁺-i-N⁺'s with i-region thicknesses, ω, from 1 μm down to 0.025 μm and with the excess noise factors down to 0.05 μm. While the results are insensitive to the precise values of input parameter for structures with ω⩾0.2 μm, this is not the case in thinner structures where the deadspace represents a significant fraction of the device. For ω<0.2 μm, the energy dependence of the ionization rate becomes increasingly important. The SMC model is tested against a full-band Monte Carlo model (FBMC) by comparing the mean distance between ionization events and the probability density functions, which are effectively the histograms of distances between ionization events, for equivalent material parameters. The good agreement between these suggests that the SMC, with a relatively small number of fitting parameters and much faster calculation times than the FBMC, is a useful tool for device simulation and interpreting experimental results     

Avalanche multiplication noise characteristics in thin GaAs p+-i-n+ diodes

Avalanche noise measurements have been performed on a range of homojunction GaAs p⁺-i-n⁺ and n⁺-i-p ⁺ diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise     

Impact ionization characteristics of III-V semiconductors for awide range of multiplication region thicknesses

Recently, an impact ionization model, which takes the nonlocal nature of the impact ionization process into account, has been described. This model incorporates history-dependent ionization coefficients. Excellent fits to experimental gain and noise measurements for GaAs were achieved using an effective field approach and simple analytical expressions for the ionization probabilities. In the paper, we briefly review the history-dependent model and apply it to Al_0.2 Ga_0.8As, In_0.52Al_0.48As and InP avalanche photodiodes. For the study, the gain and noise characteristics of a series of homojunction avalanche photodiodes with different multiplication thicknesses were measured and fit with the history-dependent model. A “size-effect” in thin (<0.5 μm) multiplication regions, which is not adequately characterized by the local-field avalanche theory, was observed for each of these materials. The history-dependent model, on the other hand, achieved close agreement with the experimental results     

Improved germanium avalanche photodiodes

New kinds of germanium avalanche photodiodes with n+-n-p and p+-n structures were devised for improved excess noise and high quantum efficiency performance. Multiplication noise, quantum efficiency, and pulse response were studied and compared with those of the conventional n+-p structure diode. Multiplication noise of the new type of diodes were measured in the wavelength range between 0.63 and 1.52 μm. The effective ionization coefficient ratio of the p+-n diode was lower than unity at a wavelength longer than 1.1 μm and 0.6-0.7 at 1.52 μm, and that of the n+-n-p diode was 0.6-0.7 in the whole sensitive wavelength region. Response times were evaluated by using a mode-locked Nd:YAG laser beam and a frequency bandwidth wider than 1 GHz was estimated. Receiving optical power levels were compared with each other using parameters measured in this study.     

Investigation of the electron transfer characteristics inmulti-δ-doped GaAs FET's

GaAs field-effect transistors (FET's) utilizing multiple δ-doping profiles to generate different shape of equivalent channels were demonstrated. The proposed structures containing three different triple-δ-doping profiles were grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). The theoretical and experimental results in the triple-δ-doped GaAs structures exhibit much superior device performance than that of conventional uniform-doped GaAs structure. Besides, the proposed structures with graded-like δ-doping profiles show significantly improved linearity of transfer characteristics when compared to that without graded-like triple-δ-doping structure. The structure also revealed an extrinsic transconductance as high as 180 mS/mm for a gate length of 2 μm     

Spreading-resistance temperature sensor on silicon-on-insulator

A spreading-resistance temperature (SRT) sensor is fabricated on silicon-on-insulator (SOI) substrate and achieves promising characteristics as compared with similar SRT sensor on bulk silicon wafers. Moreover, experimental results show that the maximum operating temperature of thin-film (1.2 μm) SOI SRT sensor can reach 450°C, much higher than 350°C of thick-film (10 μm) SOI SRT sensor under the same current level. With complete oxide isolation, this sensor structure can be potentially used in low power integrated sensors operating at temperatures as high as 450°C     

Switched capacitor compatible minimum-maximum function

A new block for the implementation of the function is presented. It is based on structures commonly used in SC circuits and is fully compatible with this approach. The circuit was realised in a 1.2 μm standard CMOS technology. The experimental results show good agreement with the predicted results     

Diode-pumped Nd:YAG laser producing 122-W CW power at 1.319 μm

A high-power diode-pumped Nd:YAG laser oscillating at a wavelength of 1.319 μm is reported. A 122-W CW laser beam with an M2 factor of 35 has been achieved with an optical efficiency of 19.6%. The lasing characteristics, including thermal lensing, at 1.319 μm are compared with those at 1.06 μm. Under lasing conditions, the focal length of thermal lensing at 1.319 μm decreases by 25% and increases by 15% at 1.06 μm with respect to the nonlasing conditions. Based on the experimental results, the heat dissipation in an Nd:YAG rod is discussed with reference to nonradiative transitions from the upper laser level     

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n⁺-p⁺ spacing L longer than 8 μm, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 μm     

Efficient coupling between annealed K+-Na+ion-exchanged channel waveguides and 10/125 single-mode fibers atλ=1.321 μm

The process of thermal annealing of K⁺-Na⁺ ion-exchanged channel waveguides has been studied with the aim of optimizing their coupling efficiency with commercial single-mode fibers at λ=1.321 μm. Waveguides obtained in soda-lime glass slides, with mask apertures ranging between 13.4 and 2.6 μm, were characterized before the annealing by combining nearfield measurements and an etching procedure. The experimental results were successfully compared with a theoretical model based on the variational principle. The refractive index distribution of K⁺-Na⁺ ion-exchanged channel waveguides supporting one or a low number of modes was given: compared to the corresponding slab case, the refractive index step Δn_o remained constant, while the waveguide depth was lower. The thermal annealing process of the channels was then performed and modeled by means of the standard diffusion theory. As a result, the channel fabrication parameters for optimum guide-fiber coupling could be predicted: 0.23-dB mode mismatch losses were measured between the optimized channel and a commercial 10/125 single-mode fiber, at λ=1.321 μm     

Transfer-matrix dynamic model of partly gain-coupled 1.55 μm DFBlasers with a strained-layer MQW active grating

A dynamic model for partly gain-coupled 1.55 μm MQW DFB lasers consisting of etched strained-layer multiquantum wells is presented. For the modulation and noise characteristics of DFB lasers, analytical expressions which take into account both the longitudinal distribution of laser parameters and carrier transport effects are derived for the first time using the transfer-matrix method. As a numerical example, the relaxation oscillation frequency is compared to experimental results, and reasonable agreements are obtained between the theory and experiment     

A very short planar silica spot-size converter using a nonperiodicsegmented waveguide

To reduce the coupling loss of a fiber-to-ridge waveguide connection, a planar silica spot-size converter for a wavelength of 1.55 μm is implemented in the form of a nonperiodic segmented waveguide structure with irregular tapering. A simple single-step lithography process is sufficient for the fabrication of the planar structures. An evolutionary algorithm has been successfully applied for the optimization. The simulated results obtained with a three-dimensional (3-D) finite difference beam propagation method (FD-BPM) program are compared with measurements of implemented couplers, showing very good agreement. A waveguide-to-fiber coupling efficiency improvement exceeding 2 dB per converter is shown. Structures obtained with this approach are very short (~140 μm) and simple to integrate on the same wafer with other planar structures such as phased arrays or ring resonator structures     

Estimation of dispenser cathode surface temperature of a practicalpotted heater cathode assembly

The heat transfer through the porous and/or infiltrated potted heater-cathode structure is simulated by a numerical model. The model includes heat conduction through a porous potting having isometric pore shape and uniform size (310 μm in alumina potting and 20 μm in tungsten cathode pellet), imperfect interface heat transfer effect and radiative boundaries. In addition to the transient study, a steady-state analysis, using the numerical model has also been done for a commercial Spectra-Mat cathode. The predicted results have been compared with the experimental measurements and are found to be in good agreement     

Technology challenges for integration near and below 0.1 μm

Technology challenges for silicon integrated circuits with a design rule of 0.1 μm and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 μm currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 μm which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 μm technology. 0.1 μm technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 μm are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 μm are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 μm is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput     

Two-dimensional numerical analysis of lasing characteristics forself-aligned structure semiconductor lasers

Lasing characteristics in 0.78 μm AlGaAs-GaAs self-aligned structure (SAS) lasers are calculated on the basis of a newly developed two-dimensional analytical method. The calculated results are compared in detail with experimental results for MOVPE (metalorganic vapor phase epitaxial) grown SAS lasers. It is shown that calculated results agree well with experimental results, and that the newly developed two-dimensional simulator is very effective in calculating actual lasing characteristics accurately. The optimum design conditions for AlGaAs-GaAs SAS lasers obtained from experimental and calculated results are discussed     

Impact ionization and transport in the InAlAs/n+-InPHFET

We have carried out an experimental study exploring both impact ionization and electron transport in InAlAs/n⁺-InP HFET's. Our devices show no signature of impact ionization in the gate current, which remains below 17 μA/mm under typical bias conditions for L_g=0.8 μm devices (60 times lower than for InAlAs/InGaAs HEMT's). The lack of impact ionization results in a drain-source breakdown voltage (BV_DS) that increases as the device is turned on, displaying an off-state value of 10 V. Additionally, we find that the channel electron velocity approaches the InP saturation velocity of about 10⁷ cm/s (in devices with L_g<1.6 μm) rather than reaching the material's peak velocity. We attribute this to the impact of channel doping both on the steady-state peak velocity and on the conditions necessary for velocity overshoot to take place. Our findings suggest that the InP-channel HFET benefits from channel electrons which remain cold even at large V_GS and V_DS making the device well-suited to power applications demanding small I_G, low g_d, and high BV_DS     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V