Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.     

High-density MIM capacitors using Al2O3 andAlTiOx dielectrics

We have investigated the electrical characteristics of Al₂ O₃ and AlTiO_x MIM capacitors from the IF (100 KHz) to RF (20 GHz) frequency range. Record high capacitance density of 0.5 and 1.0 μF/cm² are obtained for Al₂ O₃ and AlTiO_x MIM capacitors, respectively, and the fabrication process is compatible to existing VLSI backend integration. However, the AlTiO_x MIM capacitor has very large capacitance reduction at increasing frequencies. In contrast, good device integrity has been obtained for the Al₂O₃ MIM capacitor as evidenced from the small frequency dependence, low leakage current, good reliability, small temperature coefficient, and low loss tangent     

Atomic layer deposition of high capacitance density Ta2O5-ZrO2 based dielectrics for metal-insulator-metal structures

We have investigated electrical properties of laminated atomic layer deposited films: ZrO₂-Ta₂O₅, ZrO₂-Nb₂O₅-Ta₂O₅, ZrO₂-Ta_xNb_1−xO₅ and Ta₂O₅-Zr_xNb_yO_z. Even though the capacitances of laminates were often higher compared to films of constituent materials with similar thickness, considerably higher charge storage factors, Q, were achieved only when tetragonal ZrO₂ was stabilized in ZrO₂-Ta₂O₅ laminate and when the laminate thickness exceeded 50 nm. The decreased Q values in the case of most laminates were the result of increased leakage currents. In the case of thinner films only Ta₂O₅-Zr_xNb_yO_z stack possessed capacitance density and Q value higher than reference HfO₂. Concerning the conduction mechanisms, in the case of thinner films, the Ta₂O₅ or Ta_xNb_1−xO₅ apparently controlled the leakage either by Richardson-Schottky emission or Poole-Frenkel effect.     

Stack gate PZT/Al2O3 one transistorferroelectric memory

We have developed a single transistor ferroelectric memory using stack gate PZT/Al₂O₃ structure. For the same ~40 Å dielectric thickness, the PZT/Al₂O₃/Si gate dielectric has much better C-V characteristics and larger threshold voltage shift than those of PZT/SiO₂/Si. Besides, the ferroelectric MOSFET also shows a large output current difference between programmed on state and erased off state. The <100 us erase time is much faster than that of flash memory where the switching time is limited by erase time     

Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide

A method called strain-temperature stress was adopted in this work to improve the quality of ultra-thin oxide on both MOS(p) and MOS(n) capacitors. MOS structures were baked at 100 °C under externally applied mechanical stress. Reduced gate leakage current, reduced interface trap density (D_it), and improved time-dependent-dielectric-breakdown (TDDB) characteristics were observed after tensile-temperature stress treatment without increasing the oxide thickness. On the contrary, compressive-temperature stress resulted in a degraded performance of MOS capacitors. Consequently, the tensile-temperature stress method is suggested as a possible technique to enhance the ultra-thin oxide quality of MOS structure.     

MgO-Y_2O_3对热压烧结Al_2O_3性能的影响

以高纯的硫酸铝氨分解的无定形Al2O3为原料,MgO-Y2O3为烧结助剂,在N2气氛下热压烧结制备Al2O3陶瓷。研究了烧结助剂掺量对Al2O3材料的相组成、显微结构、烧结性能、力学性能、热导率和介电性能的影响。结果表明:所制Al2O3陶瓷具有细晶的显微结构特征和超高的抗弯强度。随着MgO-Y2O3掺量的增加,晶粒尺寸、抗弯强度和热导率先增大后减小,而介电损耗则呈现先减小后增大的变化规律。当MgO和Y2O3掺量均为质量分数2%时,Al2O3陶瓷呈现为较佳的综合性能:抗弯强度达最大值为603 MPa,热导率为36.47 W.m–1.K–1,介电损耗低至6.32×10–4。     

Influence of passivating interlayer on Ge/HfO2 and Ge/Al2O3 interface band diagrams

The energy band alignment between Ge, HfO₂ and Al₂O₃ was analyzed as influenced by passivating interlayers (ILs) of different composition (GeO₂, Ge₃N₄, Si/SiO_x). From internal photoemission and photoconductivity experiments we found no IL-sensitive dipoles at the Ge/HfO₂ interfaces, the latter being universally characterized by conduction and valence band offsets of 2.1 and 3.0 eV, respectively. However, in the case of HfO₂ growth using H₂O-based atomic layer deposition, the Ge oxide IL appears to have a narrower bandgap, 4.3 eV, than the 5.4–5.9 eV gap of bulk germania. Accordingly, formation of this IL yields significantly reduced barriers for hole and, particularly, electron injection from Ge into the insulator. Changing to a H-free process for HfO₂ and Al₂O₃ deposition suppresses the formation of the narrow-gap Ge oxide.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Initial leakage current related to extrinsic breakdown in HfO2/Al2O3 nanolaminate ALD dielectrics

Multiple successive breakdown events are reported for HfO₂/Al₂O₃ nanolaminate dielectrics grown by atomic-layer deposition. The first breakdown distribution is not a Weibull distribution and shows a long TBD tail at high failure percentiles. Analysis of the correlation between time-to-breakdown and initial current leakage allows identifying this tail with extrinsic breakdown. Screening of the data to eliminate the extrinsic tail demonstrates that the successive breakdown events are completely uncorrelated and perfectly match the successive breakdown theory. The statistical correlation between initial current and extrinsic breakdown distribution is explained in terms of variations of the unintentional interfacial SiO_x layer at the silicon substrate/dielectric interface.     

Optimization of Al2O3/ZrO2 nanolaminate structure for thin-film encapsulation of OLEDs

We report thin-film moisture barriers based on Al₂O₃/ZrO₂ nanolaminates grown by ALD for an encapsulation of OLEDs. In order to optimize the moisture-barrier performance of the nanolaminates, the most important factors affecting the performance were sought by measuring WVTR of the nanolaminates via an electrical Ca test. We found out that both the number of interfaces in the nanolaminates and the thickness of ZrO₂ in a unit layer were responsible for the performance. By optimizing the nanolaminate structure, the moisture-barrier performance was enhanced up to 350% from a single layer of the same thickness. The WVTR of 30-nm-thick optimized nanolaminate barrier was 2 × 10⁻⁴ g/(m² day) or less at ambient condition. A storage-lifetime measurement of an OLED with a 100-nm-thick encapsulation layer showed that it could exceed 70,000 h if stored at ambient condition.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs

New ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO₂ and amorphous phase Al₂O₃ in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 Å and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Layered Al2O3-TiO2 compositedielectric resonators

Aluminium oxide displays a very low tanδ at microwave frequencies. It also possesses a remarkably high thermal conductivity, ideal for heat dissipation in high power satellite filters. However, its temperature coefficient of the resonant frequency (τ_f) is approximately 60 ppm/K. It is shown that the application of a film of titanium oxide which has a T_f of opposite sign (45O ppm/K) produces a composite in which the τ_f can be tuned to be zero over a wide temperature range. The tanδ of the composite at zero T_f is 3.3×10⁵ (Q=30000) at room temperature and at 10 GHz     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RFfrequency range

We have characterized the capacitance and loss tangent for high-k Al₂O₃ and AlTiO_x gate dielectrics from IF (100 KHz) to RF (20 GHz) frequency range. Nearly the same rate of capacitance reduction as SiO₂ was demonstrated individually by the proposed Al₂O₃ and AlTiO_x gate dielectrics as frequency was increased. Moreover, both dielectrics preserve the higher k better than SiO₂ from 100 KHz to 20 GHz. These results suggest that both Al₂O₃ and AlTiO_x are suitable for next generation MOSFET application into RF frequency regime     

Improving electrical characteristics of W/HfO2/In0.53Ga0.47As gate stacks by altering deposition techniques

The effects of controlling InGaAs substrate temperature during electron beam deposition of HfO₂ on electrical characteristics of W/HfO₂/n-In_0.53Ga_0.47As capacitors are investigated. It is found that by depositing a thin HfO₂ layer at the interface when substrate temperature is raised to 300 °C, frequency dispersion at depletion and accumulation conditions is reduced and interface state density is lowered regardless of the HfO₂ thickness. Cross-sectional transmission electron microscopy images have revealed that the formation of mesoscopic voids in the InGaAs substrate near the interface is suppressed with HfO₂deposition at 300 °C at the interface. A band diagram with an additional bulk trap energy level has been proposed to explain the frequency dispersion and conductance peaks at accumulation condition.     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

Electrical and interfacial characteristics of nanolaminate (Al2O3/ZrO2/Al2O3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al₂O₃/ZrO₂/Al₂O₃ high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al₂O₃ (2.5 nm)/ZrO₂ (4.5 nm)/Al₂O₃ (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.     

SrO capping effect for La2O3/Ce-silicate gate dielectrics

The chemical bonding states and electrical characteristics of SrO capped La₂O₃/CeO_x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm²/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.