GaAs MESFET ring oscillator on Si substrate

GaAs MESFET ring oscillators were fabricated on a Si substrate and successfully operated. Epitaxial techniques to grow a GaAs layer on a Si substrate were investigated. The device-quality GaAs epitaxial layer was obtained by introducing a Ge layer (by ionized cluster-beam deposition) and alternating GaAs/GaAIAs layers (by MOCVD). The typical transconductance of 140 mS/mm was obtained for the FET with a 0.5 µm × 10 µm gate. The minimum delay time was 66.5 ps/ gate at a power consumption of 2.3 mW/gate.     

Heteroepitaxy of HgCdTe(112) infrared detector structures on Si(112) substrates by molecular-beam epitaxy

High-quality, single-crystal epitaxial films of CdTe(112)B and HgCdTe(112)B have been grown directly on Si(112) substrates without the need for GaAs interfacial layers. The CdTe and HgCdTe films have been characterized with optical microscopy, x-ray diffraction, wet chemical defect etching, and secondary ion mass spectrometry. HgCdTe/Si infrared detectors have also been fabricated and tested. The CdTe(112)B films are highly specular, twin-free, and have x-ray rocking curves as narrow as 72 arc-sec and near-surface etch pit density (EPD) of 2 × 10⁶ cm⁻² for 8 μm thick films. HgCdTe(112)B films deposited on Si substrates have x-ray rocking curve FWHM as low as 76 arc-sec and EPD of 3-22 × 10⁶ cm⁻². These MBE-grown epitaxial structures have been used to fabricate the first high-performance HgCdTe IR detectors grown directly on Si without use of an intermediate GaAs buffer layer. HgCdTe/Si infrared detectors have been fabricated with 40% quantum efficiency and R₀A = 1.64 × 10⁴ Ωm₂ (0 FOV) for devices with 7.8 μm cutoff wavelength at 78Kto demonstrate the capability of MBE for growth of large-area HgCdTe arrays on Si.     

Monolithic microwave amplifiers formed by ion implantation into LEC gallium arsenide substrates

A fabrication procedure for broad-band monolithic power GaAs integrated circuits has been demonstrated which includes formation of via holes through the 100-µm-thick GaAs substrate. A selective implant of²⁹Si ions into the GaAs substrate is used to dope the FET channel region to 1.2 × 10¹⁷cm^-3. The ohmic contacts are AuGe/Ni/Pt and the gates are Ti/Pt/Au. A 1.5-µm-thick circuit pattern is achieved using metal rejection assited by chlorobenzene treatment of AZ1350J photoresist. Using undoped Czochralski wafers of GaAs pulled from a pyrolytic boron nitride crucible, integrated amplifiers have been produced which deliver 28 ± 0.7 dBm from 5.7 to 11 GHz. These chips are 2 mm × 4.75 mm × 0.1 mm thick.     

Comparison of InGaSb/InAs superlattice structures grown by MBE on GaSb, GaAs, and compliant GaAs substrates

This paper contains the characterization results for indium arsenide/indium gallium antimonide (InAs/InGaSb) superlattices (SL) that were grown by molecular beam epitaxy (MBE) on standard gallium arsenide (GaAs), standard GaSb, and compliant GaAs substrates. The atomic force microscopy (AFM) images, peak to valley (P-V) measurement, and surface roughness (RMS) measurements are reported for each sample. For the 5 μm×5 μm images, the P-V heights and RMS measurements were 37 ? and 17 ?, 12 ? and 2 ?, and 10 ? and 1.8 ? for the standard GaAs, standard GaSb, and compliant GaAs respectively. The high resolution x-ray diffraction (HRXRD) analysis found different 0^th order SL peak to GaSb peak spacings for the structures grown on the different substrates. These peak separations are consistent with different residual strain states within the SL structures. Depending on the constants used to determine the relative shift of the valance and conduction bands as a function of strain for the individual layers, the change in the InAs conduction band to InGaSb valance band spacing could range from +7 meV to −47 meV for a lattice constant of 6.1532 ?. The cutoff wavelength for the SL structure on the compliant GaAs, control GaSb, and control GaAs was 13.9 μm, 11 μm, and no significant response, respectively. This difference in cutoff wavelength corresponds to approximately a −23 meV change in the optical gap of the SL on the compliant GaAs substrate compared to the same SL on the control GaSb substrate.     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.     

GaAs solar cells grown on Si substrates for space use

GaAs single‐junction and InGaP/GaAs multi‐junction thin‐film solar cells fabricated on Si substrates have great potential for high‐efficiency, low‐cost, lightweight and large‐area space solar cells. Heteroepitaxy of GaAs thin films on Si substrates has been examined and high‐efficiency GaAs thin‐film solar cells with total‐area efficiencies of 18·3% at AM0 and 20·0% at AM 1·5 on Si substrates (GaAs‐on‐Si solar cells) have been fabricated. In addition, 1‐MeV electron irradiation damage to GaAs‐on‐Si cells has been studied. The GaAs‐on‐Si cells are found to show higher end‐of‐life efficiency than the conventional GaAs cells fabricated on GaAs substrates (GaAs‐ on‐GaAs cells) under high‐fluence 1‐MeV electron irradiation of more than 1 × 10¹⁵ cm⁻². The first space flight to make use of them has been carried out. Forty‐eight 2 × 2 cm GaAs‐on‐Si cells with an average AM0 total‐area efficiency of 16·9% have been evaluated in the Engineering Test Satellite No.6 (ETS‐VI). The GaAs‐on‐Si cells have been demonstrated to be more radiation‐resistant in space than GaAs‐on‐GaAs cells and 50, 100 and 200‐μm‐thick Si cells. These results show that the GaAs‐on‐Si single‐junction and InGaP/GaAs‐on‐Si multi‐junction cells have great potential for space applications. Copyright © 2001 John Wiley & Sons, Ltd.     

Molecular beam epitaxial growth of gaas on gadolinium-gallium garnet

Single-crystal GaAs has been grown by molecular beam epitaxy on Gd₃Ga₅0₁₂ (GGG) using an InAs buffer layer and an InAs/GaAs multilayer structure between the GGG and the GaAs. The x-ray diffraction spectrum shows that both the InAs and GaAs epitaxial layers are oriented in the (111) direction when grown on a (100) GGG substrate. The unintentionally doped InAs layers aren-type and have donor concentrations in the range of 7 × 10¹⁶ to 2 × 10¹⁸ cm^-3 which vary inversely with growth temperature. The corresponding carrier mobilities vary from 3.5 × 10³ to 1 × 10³ cm²/V s. The GaAs was also found to be conducting. The 77-K photoluminescence (PL) spectrum of the GaAs grown on the GGG differs from that of homoepitaxial GaAs in that the heteroepitaxial GaAs PL intensity is approximately 50 times lower, its linewidth is five times broader, and its peak energy is blue shifted by 10 meV.     

Anti-phase domain-free growth of GaAs on offcut (001) Ge wafers by molecular beam epitaxy with suppressed Ge outdiffusion

The nucleation and growth of GaAs films on offcut (001) Ge wafers by solid source molecular beam epitaxy (MBE) is investigated, with the objective of establishing nucleation conditions which reproducibly yield GaAs films which are free of antiphase domains (APDs) and which have suppressed Ge outdiffusion into the GaAs layer. The nucleation process is monitored by in-situ reflection high energy electron diffraction and Auger electron spectroscopy. Several nucleation variables are studied, including the state of the initial Ge surface (single-domain 2×1 or mixed-domain 2×1:1×2), the initial prelayer (As, Ga, or mixed), and the initial GaAs growth temperature (350 or 500°C). Conditions are identified which simultaneously produce APD-free GaAs layers several microns in thickness on Ge wafers with undetectable Ge outdiffusion and with surface roughness equivalent to that of GaAs/GaAs homoepitaxy. APD-free material is obtained using either As or Ga nucleation layers, with the GaAs domain dependent upon the initial exposure chemical species. Key growth steps for APD-free GaAs/Ge growth by solid source MBE include an epitaxial Ge buffer deposited in the MBE chamber to bury carbon contamination from the underlying Ge wafer, an anneal of the Ge buffer at 640°C to generate a predominantly double atomic-height stepped surface, and nucleation of GaAs growth by a ten monolayer migration enhanced epitaxy step initiated with either pure As or Ga. We identify this last step as being responsible for blocking Ge outdiffusion to below 10¹⁵ cm⁻³ within 0.5 microns of the GaAs/Ge interface.     

Epitaxial growth and characterization of DyP/GaAs, DyAs/GaAs, and GaAs/DyP/GaAs heterostructures

There is a significant interest in the area of improving high temperature stable contacts to III-V semiconductors. Two attractive material systems that offer promise in this area are dysprosium phosphide/gallium arsenide (DyP/GaAs) and dysprosium arsenide/gallium arsenide (DyAs/GaAs). Details of epitaxial growth of DyP/GaAs and DyAs/GaAs by molecular beam epitaxy (MBE), and their characterization by x-ray diffraction, transmission electron microscopy, atomic force microscopy, Auger electron spectroscopy, Hall measurements, and high temperature current-voltage measurements is reported. DyP is lattice matched to GaAs, with a room temperature mismatch of less than 0.01% and is stable in air with no sign of oxidation, even after months of ambient exposure. Both DyP and DyAs have been grown by solid source MBE using custom designed group V thermal cracker cells and group III high temperature effusion cells. High quality DyP and DyAs epilayer were consistently obtained for growth temperatures ranging from 500 to 600°C with growth rates between 0.5 and 0.7 μm/h. DyP epilayers are n-type with electron concentrations of 3 × 10²⁰ to 4 × 10²⁰ cm⁻³, room temperature mobilities of 250 to 300 cm²/V·s, and a barrier height of 0.81 eV to GaAs. DyAs epilayers are also n-type with carrier concentrations of 1 × 10²¹ to 2 × 10²¹ cm⁻³, and mobilities between 25 and 40 cm²/V·s.     

Submicrometer fully self-aligned AlGaAs/GaAs Heterojunction bipolar transistor

A novel submicrometer fully self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) for reducing parasitic capacitances and resistances is proposed. The fabrication process utilizes SiO2sidewalls for defining base electrode width and separating this electrode from both emitter and collector electrodes. Measured common-emitter current gain β for a fabricated HBT with 0.6 × 10-µm²emitter dimension and 0.7 × 10-µm²× 2 base dimension is 26 at 9 × 10⁴-A/cm²collector current density.     

An investigation of i-AlGaAs/n-GaAs doped-channel MIS-like FET's (DMT's)—Properties and performance potentialities

Doped-channel MIS-like FET's (DMT's) based upon an i-AlGaAs/n-GaAs structure have been investigated in detail for the purpose of clarifying their properties and performance potentialities. The DMT is unique in having two operation modes, a depletion-layer modulation mode and an electron accumulation mode, both of which are experimentally demonstrated through capacitance-voltage characteristics. Analytical and experimental results shows that the maximum drain current IDSmaxis more than 2.5 times that for a conventional n-AlGaAs/GaAs 2DEGFET. gmmaxand IDsmaxvalues obtained for 0.5- µm gate DMT's are very high, 310 mS/mm (410 mS/mm) and 650 mA/mm (800 mA,/mm) at 300 K (77 K), respectively, fmaxis 48 GHz. fTis as large as 45 GHz, which is the best data ever reported in 0.5-µm gate FET's. Moreover, the estimated electron saturation velocity is outstandingly large, 1.5 × 10⁷cm/s (2 × 10⁷cm/s) at 300 K (77 K), even for a thin GaAs channel layer with a 3 × 10¹⁸cm^-3doping level, while Hall electron mobility is not reasonably so high, being typically 1850 cm²/V . s (1650 cm²/V . S). Preliminary power performances are also studied at 28.5 GHz. An 18-dBm (225-mW/mm) saturation output power, 6.4-dB linear gain, and 15-percent power added efficiency are achieved. A further performance improvement may be easily accomplished by gate length reduction, structure optimization, and so on. Consequently, it has been proved that DMT's have great feasibility for high-speed and high-frequency high-power device applications.     

Electron-beam fabrication of submicrometer gates for a GaAs MESFET logic

A direct electron-beam lithography is applied to the fabrication of a submicrometer gate for an enhancement-mode GaAs MESFET logic. Exposure doses to produce submicrometer stripes in the positive PMMA resist on a GaAs wafer are investigated for different beam scans of a 0.1-µm-diameter spot. The resist adhesion against a GaAs etchant under the gate recessing is tested to make a fine control of an epitaxial layer thickness with good results. A propagation delay of 64 ps with an associated power consumption of 0.4 mW is obtained with a 0.5 × 20-µm-gate GaAs MESFET, which demonstrates the fastest speed among the enhancement-mode logics.     

Nonthreshold logic ring oscillators implemented with GaAs/(GaAl)As heterojunction bipolar transistors

The first nonthreshold logic (NTL) ring oscillators implemented with GaAs/(GaAl)As heterojunction bipolar transistors (HBT's) are reported. Propagation delay times down to 52 ps per gate were achieved, using transistors with emitter dimensions of 1.2 µm × 5 µm. Numerical simulations of the circuits were also done, which agreed closely with the experimental results.     

Electrooptic effect in CdTe at 23.35 and 27.95 microns

The unlamped electrooptic coefficient r41of high-purity CdTe has been measured at 23.35 and 27.95 micros in the far infrared. The values obtained for n0³r41are 9.4 × 10^-11m/V at 23.35 µ and 8.1 × 10^-11m/V at 27.95 µ. Using previously reported values for n0, the electrooptic coefficients are found to be 5.5 × 10^-12m/V at 23.35 µ and 5.0 × 10^-12m/V at 27.95 µ. These measurements extend the region of observed electrooptic effect from 16 µ, previously obtained using GaAs, to 28 µ using CdTe.     

Channeling depth distributions of Be and Si in GaAs as a function of implantation energy and fluence

Be and Si are commonly employed p- and n-type respectively dopants, implanted in GaAs. Channeled implantation produces deeper and sharper profiles than standard random implants. To employ channeling, we need to know how the profile shape, depth, and doping density vary with implantation energy and fluence, and what maximum density can be achieved. This work shows how channeling profiles in the direction of GaAs vary with energy and fluence for room temperature channeling. Data are shown for fluences of 3 × 10¹², 3 × 10¹³, and 3 × 10¹⁴cm^-2and energies of 40, 75, 150, and 300 keV. The deep channeling profile saturates for 150 keV Be just below a fluence of 3 × 10¹⁴cm^-2and a density of about 4 × 10¹⁷cm^-3can be achieved at depths of about 1 to 3 µm for energies from 75 to 300 keV. The maximum density for 150 keV Si for room temperature channeling is about 4 × 10¹⁶cm^-3and occurs at depths from 1 to 4 µm in the energy range from 40 to 300 keV.     

Al_xGa_(1-x)As/GaAs调制掺杂结构的MBE优化工艺生长

通过对MBE工艺中影响GaAs和AlGaAs材料质量的生长关键工艺实验研究,优化了MBE生长AlxGa1-xAs/GaAs调制掺杂结构工艺。用GEN-ⅡMBE设备生长AlxGa1-xAs/GaAs调制掺杂结构材料,得到了高质量的AlxGa1-xAs/GaAs调制掺杂结构材料。用范德堡法研究材料特性,得到材料参数的典型值:二维电子气浓度在室温时为5.6×1011cm-2,电子迁移率为6000cm2/V·s;在77K低温时浓度达3.5×1011cm-2,电子迁移率为1.43×105cm2/V·s。用C-V法测量其浓度分布表明,分布曲线较陡。典型的器件应用结果为:单管室温直流跨导达280mS/mm,在12GHz时均有8dB以上的增益。     

Growth of InAs-AlSb quantum wells having both high mobilities and high concentrations

Low-temperature mobilities in InAs-AlSb quantum wells depend sensitively on the buffer layer structures. Reflection high energy electron diffraction and x-ray diffraction show that the highest crystalline quality and best InAs transport properties are obtained by a buffer layer sequence GaAs → AlAs → AlSb → GaSb, with a final GaSb layer thickness of at least 1 μm. Using the improved buffer scheme, mobilities exceeding 600,000 cm²/Vs at 10 K are routinely obtained. Modulation δ-doping with tellurium has yielded electron sheet concentrations up to 8 × 10¹² cm⁻² while maintaining mobilities approaching 100,000 cm²/Vs at low temperatures.     

Reduction of extrinsic base resistance in GaAs/AlGaAs heterojunction bipolar transistors and correlation with high-frequency performance

Improved high-frequency performance in GaAs/AlGaAs heterojunction bipolar transistors (HBT's) by reduction of extrinsic base resistance is demonstrated. A new self-aligned process which is very simple, yet capable of producing 0.25-µm emitter-to-base contact gaps, is described. By the use of AuBe, we have also been able to produce contact resistances to p-type GaAs (p = 5 × 10¹⁸) as low as 1.2 × 10^-7Ω.cm². This is the lowest value reported to p-type GaAs considering the relatively low doping levels used. By employing these techniques, we have produced HBT's with 2.5-µm-wide emitters having current gain cutoff frequencies fTthat appear to be greater than 35 GHz and maximum oscillation frequenciesf_{max}of 22 GHz.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).