40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function‐safe architecture is proposed for a fault‐tolerance system such as an electronics system for autonomous cars. The general‐purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self‐recovering cache and dynamic lockstep function. The function‐safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28‐nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function‐safe design can have ISO26262 ASIL‐D with the single‐point fault‐tolerance rate of 99.64%.     

A code-pattern-driven digital background calibration technique for SAR ADCs

The article presents the buck converter for the application on headlights of vehicle with chip-level design. The LED components are used as for lighting source, which near/far lights are controlled with high-current switching circuit in the chip. The level-shift circuit and its current driver is proposed to control the input of high-voltage power MOS. The bypass method is presented to reduce the transient time as load current changes suddenly. The input voltage widely ranges from 8 to 21 V while keeping a stable output voltage with 6 V. The chip current can output from 20 to 1500 mA with excellent regulation. This chip had been implemented with TSMC0.25 µm HV- process, and the size of the circuit layout is about 8.6 mm², where includes power switch and far/near lighting switches. Measurements show that peak efficiency can achieve 86.3%. The power regulation is excellent, where the load regulation is only 0.3%, and the line regulation is only 0.5%.

     

Comprehensive characterisation and analysis of PV module performance under real operating conditions

The specifications of photovoltaic modules show performance under standard testing conditions (STC), but only limited information relating to performance at non‐STC conditions. While performance is affected by irradiance, temperature, spectral composition of irradiance, angle‐of‐incidence of the irradiance and other parameters, specifications only partly give detail to consumers or retailers about the effect of irradiance and temperature. In this study, we characterise and analyse the performance of eight different, commercially available photovoltaic modules. We establish the effect of four different parameters on module performance: irradiance, temperature, spectral composition of irradiance (via the parameter average photon energy) and angle‐of‐incidence, by performing linear and nonlinear optimisation of physical or empirical models. Furthermore, we characterise the operating conditions and analyse the seasonal and annual development and contribution of the four parameters to energy losses or gains relative to STC operating conditions. We show a comprehensive way of presenting the deviation of performance from STC, combining the variation in operating conditions and the resulting variation in performance. Our results show that some effects on performance are attributable to the semiconductor material used in the modules (spectral composition and temperature), while especially angle‐of‐incidence effects seem more related to the type of glass used on as the front cover of the module. Variation in irradiance and module temperature generally affect performance the strongest, resulting in a performance effect ranging from  + 2.8% to  − 3.2% and  − 0.5% to  − 2.2%, respectively. The combined effect of all parameters results in an annual yield deviation ranging from  + 1.2% to  − 5.9%. © 2016 The Authors. Progress in Photovoltaics: Research and Applications published by John Wiley & Sons Ltd.     

A 1.1 V 6.2 mW,wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5–6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below −8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm².     

An embedded 32-b microprocessor core for low-power andhigh-performance applications

An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-μm CMOS process implementing the ARM^TM V.5TE instruction set is described. The core described is the first implementation of the Intel XScale Microarchitecture^TM. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm² in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range     

基于MAX7456的视频电子分划叠加系统设计

根据视频图像电子叠加原理,完成了屏幕存储映射方式的电子十字分划线及提示符的叠加。该系统由STC12C5608单片机、MAX7456视频叠加芯片、电源电路组成。外围电路简单,实现了叠加图像与场景图像同显、十字分划位置可控二维满屏移动,便于在轻武器上安装使用。该系统在武装机动平台控制系统上得到应用。     

A cost-effective three axis CMOS accelerometer combining micromachining and digital technology

In this paper, a three axis accelerometer is successfully developed by a mixing-mode chip design using CMOS surface-micromachining technology. The chip consists of mass-spring, the analog core and the digital circuit. The vibration sensor is implemented with micro-spring to change the capacitance between two metals. The analog core detects the capacitance differential to the frequency shifting using an oscillator. The digital control is to compute the amount of acceleration to the form of digital bit. The chip can detect the acceleration to 140 g for x axis and y axis with 10-bit resolution, and from 110 g for z axis with 9 bits. The detected speed is about 4 k bits per second, for three-axis output in parallel. The chip size is about 1,400 × 1,400 um², when TSMC 0.18 um 1P6 M process is employed. This 3D accelerometer can directly connect to the digital interface with three serial-port output for the information of X, Y and Z axis.     

Direct digital-RF amplitude modulator in CMOS 90nm

Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segment-addressed resulting in a very compact 0.007 mm² chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz.     

Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels—A Showcase

In this paper, we propose a low-power VLSI implementation of H.264/AVC baseline decoder. A systematic methodology for power reduction is proposed and applied at various design abstraction levels. At the algorithm level, the computational complexity is optimized. At the architecture level, pipelining and parallelism are widely adopted to reduce the operating frequency; hierarchical memory organization optimizes power-hungry memory accesses; hardware sharing reduces the total switching capacitance. At the circuit level, the knowledge about signal statistics is exploited to reduce number of transitions; data dependent signal-gating and clock-gating are introduced which are dynamic techniques for power reduction; multiplications are reduced and optimized, while complex dividers are totally eliminated. At the physical level, cell sizing and layout are optimized for power efficiency. The VLSI implementation shows that with UMC 0.18 μm technology, the proposed design is able to decode realtime QCIF 30fps at 1.5 MHz. The decoder contains 169 k logic gates and 2.5 KB on-chip SRAM. The total chip area is 4.4 × 4.4 mm² in a CQFP 208 package. The measured power consumption is 973 μW @ 1.8 V and 293 μW @ 1.0 V. The low-power and realtime features make our design ideal for portable or mobile applications.     

Automated optimization for memory‐efficient high‐performance deep neural network accelerators

The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high‐performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high‐performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE‐array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high‐performance DNN accelerators.     

A low power sigma-delta modulator for dual-mode wide-band receiver

This work presents a low power cascaded sigma-delta modulator for GSM and WCDMA applications. The proposed modulator has the characteristics of wide bandwidth for WCDMA applications and low distortion in the low frequency band for GSM applications. Low-distortion and interpolative techniques are used in this modulator to enhance the performance. The low-distortion technique has not only the swing-suppressing characteristic, but it can reduce the power consumption. Moreover, the resolution can be improved even under non-linearity effects. An experimental chip is implemented in the standard 0.18-μm 1P6M CMOS technology. The measurements indicate a dynamic range of 76/68 dB and a peak signal to noise plus distortion ratio of 70/61 dB for GSM/WCDMA applications. The core area is 1 × 1.4 mm² and the power consumption is 10.5/28 mW for GSM/WCDMA at 1.8 V.     

6‐GHz‐to‐18‐GHz AlGaN/GaN Cascaded Nonuniform Distributed Power Amplifier MMIC Using Load Modulation of Increased Series Gate Capacitance

A 6‐GHz‐to‐18‐GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a 0.25‐μm AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power‐added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse‐mode condition of a 100‐μs pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.     

A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture

An analog computing-based systolic architecture which employs multiple neuroprocessors for high-speed early vision processing is presented. For a two-dimensional image, parallel processing is performed in the row direction and pipelined processing is performed in the column direction. The mixed analog/digital design approach is suitable for implementation of electronic neural systems. Local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Inter-processor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to achieve direct scalability in neural network size. For demonstration purposes, a compact and efficient VLSI neural chip that includes multiple neuroprocessors for high-speed digital image restoration is designed. Measured results of the programmable synapse, and statistical distribution of measured synapse conductances are presented. Based on these results, system-level analyses at 8-bit resolution are conducted. A 8.0×6.0-mm ² chip from a 1.2-µm CMOS technology can accommodate 5 neuroprocessors and the speed-up factor over the Sun-4/75 SPARC workstation is around 450. This chip achieves 18 Giga connections per second.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by TRW Inc., Samsung Electronics Co., Ltd., and NKK Corp.     

基于单片机的电磁控制运动装置

电磁控制运动装置是一种单摆式的运动装置,由电磁控制部分和摆杆部分组成。其电磁控制部分由电源模块、线圈驱动模块、控制模块、按键模块、显示模块、摆动模块等组成,核心元件是8位的STC12C5A60S2单片机,通过单片机控制摆杆的角度和周期。     

基于单片机的非接触式照明线路定位仪器设计

为了能够对铺设在墙壁中的照明线路进行定位,采用现代电磁学理论以及单片机为代表的微机控制技术设计非接触式照明线路定位仪器。仪器主要有主控部分、电磁探测部分、显示部分、电源部分等组成。主控板以STC89C516单片机为控制核心,电磁探测部分以74HC14触发器构成电磁感应电路,显示部分运用LCD12864显示模块,电源部分运用LM2596的3A电流输出降压开关型集成稳压芯片。同时设计中考虑可能存在的各种干扰因素,采用了软硬件结合的抗干扰技术,提高了系统的稳定性。最后对系统进行了模拟性能测试,测试结果表明系统性能良好。     

Sputtered Zn(O,S) buffer layers for CIGS solar modules—from lab to pilot production

Sputtering of Zn(O,S) from ZnO/ZnS compound targets has been proven to be a promising buffer layer process for Cd‐free CIGS modules due to easy in‐line integration, low cost and high efficiency on lab scale. In this publication, we report on successful upscaling of the lab process to pilot production. A record aperture efficiency of 13.2% has been reached on a 50 × 120 cm² sized module. Neither a non‐doped ZnO layer nor additional annealing steps are required. Moreover, this very reproducible process yields a standard deviation comparable with that of the CdS base line. In contrast to lab experiments, strong performance gain after light soaking has been observed. The light‐soak‐induced power increase depends on the preparation of the window layer. Accelerated aging tests show high stability of module power. This is confirmed by outdoor testing for 20 months. Copyright © 2017 John Wiley & Sons, Ltd.     

A low-complexity UWB RF receiver based on a novel low noise amplifier

A novel low-complexity ultra-wideband UWB receiver is proposed for short-range wireless transmission communications without considering multipath effect. The receiver chip uses a low-complexity UWB non-coherent receiving system solution with the core module composed of squarer and low-pass filter. By introducing asymmetric gate series inductance and RCL parallel negative feedback loop into the two-stage push–pull amplifier, the low-noise amplification and input impedance matching at ultra-wide bandwidth were achieved. With only two inductors and self-biased function, the chip area and power consumption can be saved largely. The proposed UWB receiver chip was fabricated in a 0.18 μm RF CMOS technology. Experimental results show that it can achieve a bandwidth of 3–5 GHz, maximum receiving symbol rate of 250 Mbps, receiving sensitivity of −80 dBm and power consumption of 36 mW, providing a low-complexity and high-speed physical implementation of the short-range high-speed wireless interconnection between electronic devices in the future.     

GaAs converters for high power densities of laser illumination

Photovoltaic power converters can be used to generate electricity directly from laser light. In this paper we report the development of GaAs PV power converters with improved conversion efficiency at high power densities. The incorporation of a lateral conduction layer (LCL) on top of the window layer resulted in a considerable gain in efficiency at high illumination levels. Additional performance improvements were obtained by using a metal electrode grid design and antireflection coating optimised for monochromatic and inhomogeneous laser light. Maximum monochromatic (810 nm) optical‐to‐electrical conversion efficiency of 54·9% at 36·5 W/cm² has been achieved. The characteristics of laser power converters with p/n and n/p polarity are discussed in this paper. Moreover, different materials and doping levels were applied in the LCL. The performance of these different device structures at high laser intensity is presented and discussed. It is shown that the lateral series resistance of the cell has a major impact on the overall device performance. Copyright © 2008 John Wiley & Sons, Ltd.     

一种新型开关电源并联供电系统的设计

采用低功耗单片机STC12C5204AD为控制核心,产生两路PWM来驱动开关管SFR9034 MOS管,结合AD反馈形成两路可控的DC-DC电源并联系统,实现稳压输出,并且能按照任意设定比例调整输出电流,有限流保护控制,工作稳定,效率高,满足实际应用要求.     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.