Reliability of Cu wire bonds in microelectronic packages

In this study the thermo-mechanical response of 25 μm Cu wire bonds in an LQFP-EPad (Low Profile Quad Flat-Exposed Pad) package was investigated by numerical and experimental means. The aim was to develop a methodology for fast evaluation of the packages, with focus on wire bond fatigue, by combining finite element analysis (FEA) and mechanical fatigue testing. The investigations included the following steps: (i) simulation of the warpage induced displacements in the encapsulated LQFP-176-Epad package due to temperature changes, (ii) reproducing the thermally induced stresses in the wire bond loops in an unmolded (non-encapsulated) LQFP package using an accelerated multiaxial mechanical fatigue testing set-up under the displacement amplitudes determined in case (i) and determination of the loading cycles to failure (N_f), (iii) FEA of the experiments performed in (ii) based on the boundary conditions determined in (i) to calculate the states of stress and strain in the wire bonds subjected to multiaxial mechanical cyclic loading. Our investigations confirm that thermal and mechanical cyclic loading results in occurrence of high plastic strains at the heat affected zone (HAZ) above the nail-head, which may lead to fatigue failure of the wire bonds in the packages. The lifetime of wire bonds show a proportional relation between the location and angle of the wire bond to the direction of loading. The calculated accumulated plastic strain in the HAZ was correlated to the experimentally determined N_f values based on the volume weighted averaging (VWA) approached and presented in a lifetime diagram (∆ d - N_f) for reliability assessment of Cu wire bonds. The described accelerated test method could be used as a rapid qualification test for the determination of the lifetimes of wire bonds at different positions on the chip as well as for related improvements of package design.     

A fast mechanical test technique for life time estimation of micro-joints

A novel accelerated mechanical testing method for reliability assessment of micro-joints in the electronic devices is presented as an alternative to time consuming thermal and power cycling test procedures. A special experimental set-up in combination with an ultrasonic resonance fatigue testing system and a laser Doppler vibrometer is used to obtain fatigue life curves of micro-joints under shear loading. Using this method fatigue life curves of Al wire bonded micro-joints were obtained up to 10⁹ number of loading cycles and discussed with regard to micro-mechanisms of the bond failure. Failure analysis of the fatigued micro-joints showed that the predominant failure mechanism of power cycling tests, bond wire lift-off, was reproduced by the mechanical testing procedure. Life time of the micro-joints was modelled using a Coffin–Manson type relationship and showed a good correlation to life time curves obtained by power cycling tests. The major advantage of the proposed fast mechanical testing method is the significant reduction of the testing time in comparison with conventional thermal and power cycling tests. Furthermore subsequent examination of the failure surface provides a reliable tool for improvement of the bonding process. The proposed high frequency fatigue testing system can be applied as a rapid qualification and screening tool for various kinds of interconnects in electronic packaging.     

Interface reliability and lifetime prediction of heavy aluminum wire bonds

In this study a high frequency mechanical fatigue testing procedure for evaluation of interfacial reliability of heavy wire bonds in power semiconductors is presented. A displacement controlled mechanical shear testing set-up working at a variable frequency of a few Hertz up to 10 kHz is used to assess the interfacial fatigue resistance of heavy Al wire bond in IGBT devices. In addition, power cyclic tests were conducted on IGBT modules for in-situ measurement of the temperature distribution in the devices and determination of the thermally induced displacements in the wire bond loops. Finite Element Analysis was conducted to calculate the correlation between the thermally and mechanically induced interfacial stresses in the wire bonds. These stress values were converted into equivalent junction temperature swings (ΔT_j) in the devices based on which lifetime curves at different testing frequencies were obtained. Comparison of the fatigue life curves obtained at mechanical testing frequencies of up to 200 Hz with the power cycling data related to the wire bond lift-off failure revealed a very good conformity in the ranges of 50 to 160 K. A lifetime prediction model for Al wire bonds in IGBT modules is suggested by which the loading cycles to failure can be obtained as a function of ΔT_j and the mechanical testing frequency. The proposed accelerated shear fatigue testing procedure can be applied for rapid assessment of a variety of interconnects with different geometries and material combinations. Decoupling of the concurrent failure mechanisms and separation of the thermal, mechanical and environmental stress factors allows a more focused and efficient investigation of the interfaces in the devices.     

Effects of metallization characteristics on gold wire bondability of organic printed circuit boards

Organic printed circuit boards (PCBs) with Au/Ni plates on bond pads are widely used in chip-on-board (COB), ball grid array (BGA), and chip-scale packages. These packages are interconnected using thermosonic gold wire bonding. The wire bond yield relies on the bondability of the Ni/Au pads. Several metallization parameters, including elemental composition, thickness, hardness, roughness, and surface contamination, affect the success of the solid state joining process. In this study, various characterization and mechanical testing techniques are employed to evaluate these parameters for different metallization schemes with varying Ni and Au layer thicknesses. The pull force of Au wires is measured as a function of plasma treatment applied before wire bonding to clean the bond pads. Close correlations are established between metallization characteristics and wire bond quality.     

Reliability model for Al wire bonds subjected to heel crack failures

In power electronic packages wire bonding is used for the electrical contact of the chips and for interconnections on the module substrate. Limiting factors for the reliability are solder fatigue and wire bond failures. In this work we investigate the material fatigue of aluminum bonding wires stressed by cyclic lateral bonding area displacement. Bond wire heel crack failures observed by experiments are found to be strongly dependent on the loop geometry. Based on a finite element model that accounts for elastic-plastic material properties, a life-time model for the Al wire (Coffin-Manson representation) is derived from the experiments.     

Crack mechanism in wire bonding joints

High voltage and high current power modules are key components for traction applications. While the modules are exposed to harsh stress conditions all over their lifetime, high reliability is of decisive importance in this field of application. In power electronic packages wire bonding is used for the electrical interconnection from the chips to the output pins. Wire bond lift-off and solder fatigue are limiting the reliability. In this work we investigate the initiation and growth of cracks in the wire bonds using finite-element analysis.     

High-temperature wire sweep characteristics of semiconductor package for variable loop-height wirebonding technology

This paper studies the elevated-temperature sweep characteristics of wire bond during the transfer molding process for semiconductor packages. The material properties of gold wire are obtained experimentally at various temperatures. A set of sweep experiments is also performed to acquire the sweep stiffness of wire bond for several bond spans and bond heights. The linearity of the load-transverse displacement curves from sweep experiments indicates that the ranges of the allowance bond pitch in most semiconductor packages may be within linear elasticity limits. The elastic numerical analysis may be applied to predict the sweep behavior of the wire bond. In order to predict the elevated temperature behavior of wire bond sweep, a methodology is proposed in this study. With the aids of geometry factor defined in Eq. (6) and the three drag force models, Lamb’s, Sherman’s and Takaisi’s, the predictions of the elevated-temperature sweep deflections of wire bond can be tested. The results show that the increase of the sweep deflections is more related to bond span than bond height.     

Fatigue life evaluation of wire bonds in LED packages using numerical analysis

Reliability of LED packages is evaluated using several tests. When a thermal shock test, which is one of the reliability tests, is conducted, the most common failure mode is wire neck breakage. In order to evaluate the wire bonding reliability of LED packages, performing the thermal shock test is time-consuming. In this paper the wire bonding reliability for LED packages is evaluated by using numerical analysis. A wire bonding lifetime model for the thermal shock test was developed, which is based on Coffin-Manson fatigue law. The model was calibrated from fatigue data of thermal shock tests and volume averaging accumulated plastic strains. The accumulated plastic strains were calculated by using finite element analysis corresponding to the test conditions. The test conditions were changed by silicones, package sizes, wire bonding diameters, heights, and lengths. The calibrated model was used to estimate the number cycle to failure so that the wire bonding reliability for the thermal shock test was evaluated by performing the numerical analysis. Furthermore, we used a response surface methodology to study the relationship between the wire loop and the accumulated plastic strain to determine the optimal wire loop. The plastic strain was a function of diameter, height and length. At the optimal point, the number of cycle to failure for the thermal shock test was suggested using the wire bonding lifetime model.     

多层芯片应用中的封装挑战和解决方案

The continuous growth of stacked die packages is resulting from the technology‘s ability to effectively increase the functionality and capacity of electronic devices within the same footprint as a single chip.The increased utilization of stacked die packages in cell phone and other consumer products drives technologies that enable multiple die stacks within a given package dimension.This paper reviews t6he technology requirements and challenges for stacked die packages.Foremost among these is meeting package height is 1.2mm for a single die package.For stacked die packages,two or more die need to fit in the same area.That means every dimension in the package has to decrease,including the die thickness.the mold cap thickness,the bond line thickness and the wire bond loop profile.The technology enablers for stacked die packages include wafer thinning,thin die attachment,low profile wire bonding,bonding to unsupported edges and low sweep molding.     

Lifetime extrapolation for IGBT modules under realistic operation conditions

In this paper a systematic approach is presented for extrapolating the lifetime due to bond wire lift-off in IGBT modules submitted to cyclic loading. Application profiles of the device are considered, as they are usually encountered in real current converters for railway traction systems. The proposed lifetime prediction scheme is based on the principle of the linear accumulation of the fatigue damage and takes into account the redundancy of the bond wires.     

Analytical approach to temperature evaluation in bonding wires andcalculation of allowable current

Wirebonding is still the most common technique being applied to device assembly. Since the entire electrical power for the chip has to be delivered through the wires, considerable current densities may occur. As a result, bond wires are heated up and in case of too excessive current wires or surrounding materials might suffer and subsequently fail. In order to increase reliability of semiconductor devices it is important to know the resultant temperature due to a given current and deduced from this, the allowable loading so that a maximum temperature will not be exceeded. In this paper universally valid formulas for steady state, single pulse and periodic loading are introduced. They are derived from the heat diffusion equation resulting from a mathematical model which is proposed for simplification. In case of ceramic packages radiation and convection effects are considered whereas conduction through the molding compound is taken into account if the wire is encapsulated in plastic. The formulas also enable comparison between the effects of heat conduction through the wire and through the molding compound. Besides, the system of differential equations considers the temperature dependence of the specific resistance and the thermal conductivity of the wire material. Corrections for very thin plastic packages and multiple bonding are suggested. The formulas have been checked by both experimental data and numerical computation by means of Finite Element Analysis     

金凸点键合工艺在国产陶瓷外壳中的应用

国产陶瓷外壳已经逐渐应用于高可靠要求的各类电子元器件的封装上。在IC封装过程中, 随着封装密度的提高,因其键合指状引线的质量难以满足键合工艺要求,为使其能达到工艺控制要求, 我们开发出一些相应的封装技术,提高了产品的可靠性。金凸点键合工艺用于提高国产陶瓷外壳键合指 上的键合引线强度有非常明显的效果,是一项较新的技术。     

A method to determine the sweep resistance of wire bonds for microelectronic packaging

Many kinds of gold wire and bond profiles have been used in wire bonding technology. To date, no solid experimental results have been available to guide the bond designer in the choice of a better looping system. A method is proposed for evaluating the sweep resistance of wire bonds during the transfer molding process. The wire sweep method was developed to obtain load-transverse displacement curves of wire bonds. The sweep stiffness of a wire bond is defined as the index of sweep resistance to drag during the transfer molding process, and can be evaluated on the basis of the load-transverse displacement curves. A wire bond with high sweep stiffness possesses a low wire sweep and sag for integrated circuit packaging. In this study, three types of wire bonds, Q-loop, S-loop and M-loop bonds, were examined to determine the sweep stiffness. The results showed that the Q-loop bond has the highest sweep stiffness for fixed bond spans and bond heights. For longer connections or crossing another chip in multi-chip module/three-dimensional packages, the M-loop bonds were affected significantly by their kinking numbers within a bond. The experimental results indicated that the M-loop bond has 13-75% better sweep resistance than the S-loop bond, depending on the bond span and bond height used.     

叠层芯片封装技术与工艺探讨

论述了在叠层芯片封装的市场需求和挑战。首先采用在LQFP一个标准封装尺寸内,贴装2个或更多的芯片,这就要求封装体内每一个部分的尺寸都需要减小,例如芯片厚度、银胶厚度,金丝弧度,塑封体厚度等,要求在叠层封装过程中开发相应的技术来解决上述问题。重点就芯片减薄,银胶控制,无损化装片,立体键合,可靠性等进行了详细的介绍。     

Evaluation of wire bonding performance, process conditions, and metallurgical integrity of chip on board wire bonds

Chip on board wire bonding presents challenges to modern wire bonding technology which include smaller, closely spaced wire bond pads; bonding to soft substrates without special processing and pad construction; and diverse first bond and second bond metallurgies. These challenges are addressed by extensive bonding accuracy tests, a design of experiments approach for optimizing wire bond process parameters, reliability testing, and detailed materials characterization of the metallurgical integrity of the wire bonds. The thermo-mechanical integrity of the wire bond interconnects was evaluated by wire pull and hot storage tests. Hot storage testing allowed for detection of samples with an electrolytic gold surface finish that was too thin, and exhibited a contamination-corrosion condition of the nickel under-plating. Other samples with an excessively thick, rough textured nickel under-plating layer exhibited poor wire bond-ability. The methodology of materials analyses of the metallurgy of the wire bond interconnects is described. The paper illustrates a wire bond lift technique that is used to inspect for cratering damage and the “area-uniformity” of gold aluminum intermetallics. An improved understanding of the wire bonding process was achieved by showing the dependence of the visual appearance of the wire bonds on wire bond process parameters.     

Study of nickel contamination on the ultrasonic bondability of gold bond finger of SD-48L packages

Contamination is a major barrier to the adhesion of solid-phase metal couples. If me-tallic impurities are present on a gold (Au) bonding surface, it can easily react with oxygen molecules in the atmosphere to form oxides. The oxides formed prevent intimate metal-metal contact which is important for bond formation. A study is carried out to investigate whether nickel (Ni) contamination can affect the ultrasonic bondability of Au bond finger of side-braze 48-lead ceramic package. Two sets of samples are used for this study. The first set comprising uncontaminated packages serves as a control group. The second set are Ni contaminated packages. The results of the study show that Ni contamination does not affect the ultrasonic bondability of the Au bond finger. A second study to ascertain the quality of the wire bonds however shows that the mean bond tensile strength of the Ni contaminated packages has weakened slightly.     

A novel decapsulation technique for failure analysis of epoxy molded IC packages with Cu wire bonds

A cost-effective and simple technique involved in the decapsulation technique of different packages with various epoxy molding compounds (EMCs) attracted a large interest for use in failure analysis of reverse engineering. In this study, we reported that the epoxies molded IC packages with Cu wire bonds were decapsulated using a mixed acid controlled by a jet etcher with minimum degradation of Cu wires and bond interfaces. It was found that the nitric acid to sulfuric acid ratio of 2:1 was the optimum recipe for the preservation of Al pad and Cu wire. We also successfully developed a process both including laser and wet treatments to solve the over-etching and corrosion problems for critical package geometries of ball grid array packages. Additionally, the various physicochemical properties of the wet etching rates for EMCs were also studied using an atomic force micro microscopy, a Kelvin probe force microscopy, and thermo-gravimetrical analyses.     

Acid Decapsulation of Epoxy Molded IC Packages With Copper Wire Bonds

Epoxy molded IC packages with copper wire bonds are decapsulated using mixtures of concentrated sulfuric acid (20%) and fuming nitric acid in an automatic decapping unit and, observed with minimal corrosion of copper wires (0.8–6 mil sizes) and bond interfaces. To attain maximum cross-linking of the molded epoxies, the post mold cured packages (175$^circ$C for 4 h) were further, aged at high temperature of 150$^circ$C for 1000 h. These packages are decapsulated using mixtures of higher ratio of concentrated sulfuric acid (40%) along with fuming nitric acid. The shear strength of copper wire bonds with 1 mil (25$mu$m) diameter of the decapsulated unit is higher than 5.5 gf/mil$^2$. The present study shows copper stitch bonds to Au, Cu, Pd, and Sn alloy plated surfaces are less affected on decapping, with a few grams of breaking load on stitch pull test, while stitch bonds on silver plated surfaces reveal lifting of wire bonds on decapping.     

Mechanical and electrical characterisation of Au wire interconnects in electronic packages under the combined vibration and thermal testing conditions

This paper concerns the reliability of thermosonically bonded 25 μm Au wires in the combined high temperature with vibration conditions, under which the tests have been carried out on wire-bonded 48-pin Dual-in-Line (DIL) High Temperature Co-fired Ceramic (HTCC) electronic packages. Mechanical, optical and electrical analysis has been undertaken in order to identify the failure mechanisms of bonded wires due to the combined testing. The results indicated a decrease in the electrical resistance after a few hours of testing as a result of the annealing process of the Au wire during testing. In general, ball shear and wire pull strength levels remained high after testing, showing no significant deterioration due to the tests under the combined high temperature and vibration conditions. However, a trend of the variation in the strength values is identified with respect to the combined conditions for all wire-bonded packages, which may be summarised as: (i) increase of the testing temperature has led to a decrease of both the shear and pull strength of the wire bonds; (ii) the mechanical behaviour of the wires is affected due to crystallisation that leads to material softening and consequently the deformation of wire.     

Bond reliability under humid environment for coated copper wire and bare copper wire

There is growing interest in Cu wire bonding for LSI interconnection due to cost savings and better electrical and mechanical properties. Conventional bare Cu bonding wires, in general, are severely limited in their use compared to Au wires. A coated Cu bonding wire (EX1) has been developed for LSI application. EX1 is a Pd-coated Cu wire to enhance the bondability.Bond reliability at a Cu wire bond under a humid environment is a major concern in replacing Au wires. The bond reliability of EX1 and bare Cu was compared in the reliability testing of PCT and UHAST (Unbiased HAST). The lifetimes for EX1 and the bare Cu in PCT testing were over 800 h and 250 h, respectively. Humidity reliability was significantly greater for EX1. Continuous cracking was formed at the bond interface for the bare Cu wire. Corrosion-induced deterioration would be the root cause of failure for bare Cu wires. The corrosion was a chemical reaction of Cu-Al IMC (InterMetallic Compound) and halogens (Cl, Br) from molding resins. EX1 improves the bond reliability by controlling diffusion and IMC formation at the bond interface. The excellent humidity reliability of the coated Cu wire, EX1 is suitable for LSI application.