Time dependent breakdown characteristics of parylene dielectric in metal–insulator–metal capacitors

In this work, we present reliability results of MIM (Metal–Insulator–Metal) capacitors fabricated with parylene as the dielectric, deposited at room temperature. We have evaluated the time dependent dielectric breakdown (TDDB) of parylene-based MIM capacitors as a function of constant DC voltage stress, area and dielectric thickness of the capacitor. Mean-time-to-failure (MTTF) of parylene evaluated at different stress voltages shows a power law distribution over the applied voltage range and device area, with MTTF driven by the number of defects. Defect density in the parylene capacitors is also reported and is calculated to be ～1.2 × 10³ defects/cm².     

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200 V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1 V even after 2000 h of serious gate voltage stresses of + 25 V and − 10 V at 150 °C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000 h under the drain voltage of 1200 V at 150 °C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

Design,development and reliability testing of a low power bridge-type micromachined hotplate

In this paper, the development and reliability of a platinum-based microheater with low power consumption are demonstrated. The microheater is fabricated on a thin SiO₂ bridge-type suspended membrane supported by four arms. The structure consists of a 0.6 μm-thick SiO₂ membrane of size 50 μm × 50 μm over which a platinum resistor is laid out. The simulation of the structure was carried out using MEMS-CAD Tool COVENTORWARE. The platinum resistor of 31.0 Ω is fabricated on SiO₂ membrane using lift-off technique. The bulk micromachining technique is used to create the suspended SiO₂ membrane. The temperature coefficient of resistance (TCR) of platinum used for temperature estimation of the hotplate is measured and found to be 2.2 × 10⁻³/°C. The test results indicate that the microhotplate consumes only 11.8 mW when heated up to 400 °C. For reliability testing, the hotplate is continuously operated at higher temperatures. It was found that at 404 °C, 508 °C and 595 °C, the microhotplate continuously operated up to 16.5 h, 4.3 h and 4 min respectively without degrading its performance. It can sustain at least 53 cycles pulse-mode of operation at 540 °C with ultra-low resistance and temperature drifts. The structure has maximum current capability of 19.06 mA and it can also sustain the ultrasonic vibration at least for 30 min without any damage.     

Structural,magnetic and electrical properties of Fe/Si system

Interface studies in metal/semiconductor systems are important due to their potential technological application in microelectronics. A total of 80 nm Fe film was deposited on Si(1 1 1) substrate using electron beam evaporation technique at a vacuum of 2×10⁻⁷ Torr. The samples were annealed at temperatures 500 and 600 °C for 1 h in 3×10⁻⁵ Torr for the formation of silicide phases. GIXRD results show a stable disilicides FeSi₂ formation at the interface at annealing temperature 600 °C. The coercivity determined from MOKE hysteresis curves for as-deposited and annealed samples are 14.91, 29.82 and 31.01 Oe. The Schottky barrier height, as estimated by the current–voltage measurement is 0.59, 0.54 and 0.49 eV for pristine and annealed samples at 500 and 600 °C, respectively, and concludes that the barrier height values as a function of the heat of formation of the silicides.     

End of life and acceleration modelling for power diodes under high temperature reverse bias stress

This work is motivated by the growing importance of lifetime modelling in power electronics. Strongly accelerated High Temperature Reverse Bias (HTRB) testing of power diodes at different stress conditions is performed until alterations and fatigue mechanisms become evident. Two categories of effects can be separated: Drifting breakdown voltage and hard failures with complete loss of blocking capability. Nevertheless the overall stress duration needed to provoke destructive failures is very high with test durations > 2500 h even at almost 230 °C and 100% rated voltage. For both mechanisms the temperature and voltage acceleration is evaluated. Especially temperature acceleration is significant in the regime of testing between 200 °C and 230 °C and an activation energy E_a in the regime > 1 eV can be deduced which is higher compared to values commonly reported in the literature. Failure analysis shows that both package and also chip related effects could contribute to the observed hard failures in HTRB stress under extreme conditions.     

Electrical properties of Π-conjugated Fe-TPP molecular solar cell device

A heterojunction device of Au/Fe-TPP/n-Si/Al was assembled by thermally evaporated deposition. The dark current density–voltage characteristics of device were investigated. Results showed a rectification behavior. Measurements of thermo electric power confirm that Fe-TPP thin film behaves as p-type semiconductors. Electronic parameters such as barrier height, diode ideality factor, series resistance, shunt resistance were found to be 0.83 eV, 1.5, 7 × 10⁵ Ω and 2 × 10¹⁰ Ω, respectively. The Au/Fe-TPP/n-Si/Al device indicates a photovoltaic behavior with an open circuit voltage V_oc of 0.52 V, short circuit current I_sc of 2.22 × 10^?6 A, fill factor FF of 0.49 and conversion efficiency 1.13% under white light illumination power 50 W/m².     

Twistable nonvolatile organic resistive memory devices

We fabricated an 8 × 8 cross-bar array-type organic nonvolatile memory devices on twistable poly(ethylene terephthalate) (PET) substrate. A composite of polyimide (PI) and 6-phenyl-C61 butyric acid methyl ester (PCBM) was used as the active material for the memory devices. The organic memory devices showed a high ON/OFF current ratio, reproducibility with good endurance cycle, and stability with long retention time over 5 × 10⁴ s on the flat substrate. The device performance remained well under the twisted condition with a twist angle up to ～30°. The twistable organic memory device has a potential to be utilized in more complex flexible organic device configurations.     

Investigation of TiO2 on AlGaAs prepared by liquid phase deposition and its application

The study explored titanium dioxide (TiO₂) on aluminum gallium arsenide (AlGaAs) prepared by liquid phase deposition (LPD) at 40 °C. The leakage current density was about 8.4 × 10^?6 A/cm² at 1 MV/cm. The interface trap density (D_it) and the flat-band voltage shift (ΔV_FB) were 2.3 × 10¹² cm^?2 eV^?1 and 1.2 V, respectively. After rapid thermal annealing (RTA) in the ambient N₂ at 350 °C for 1 min, the leakage current density, D_it, and ΔV_FB were improved to 2.4 × 10^?6 A/cm² at 1 MV/cm, 7.3 × 10¹¹ cm^?2 eV^?1, and 1.0 V, respectively. Finally, the study demonstrates the application to the AlGaAs/InGaAs metal–oxide–semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT). The results indicate the potential of the proposed device with a LPD-TiO₂ gate oxide for power application.     

The effect of heat treatments on the properties of Ti/Pt heating elements for gas sensor applications

Ti/Pt as heating element for gas sensor applications was fabricated on silicon (Si) wafer substrate. The fabricated device was subjected to heat treatment at different prescribed time periods for thermal stability. The energy dispersion spectroscopy (EDS) results of the device indicated that there were no Ti traces on the Pt surface after heat treatment at 450 °C for 3 and 4 h in an argon (Ar) atmosphere. A maximum temperature coefficient of resistance (TCR) with a value of 2.88×10^?3 K^?1 was obtained for the device with 3 h heat treatment.     

Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75°, 80°, 85° and 90°. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80° for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1×10¹⁵ to 5×10¹⁵ cm⁻³) cause increase of T-TSV capacitance by about 25 fF, −12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.     

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23×0.45 mm², while the power combiner only occupies 200×80 μm².     

Effect of elevated temperature on PCB responses and solder interconnect reliability under vibration loading

In this paper, vibration tests are conducted to investigate the influence of temperature on PCB responses. A set of combined tests of temperature and vibration is designed to evaluate solder interconnect reliability at 25 °C, 65 °C and 105 °C. Results indicate that temperature significantly affects PCB responses, which leads to remarkable differences in vibration loading intensity. The PCB eigenfrequency shifts from 290 Hz to 276 Hz with an increase of test temperature from 25 °C to 105 °C, during which the peak strain amplitude is almost the same.Vibration reliability of solder interconnects is greatly improved with temperature rise from 25 °C to 105 °C. Mean time to failure (MTTF) of solder joint at 65 °C and 105 °C is increased by 70% and 174% respectively compared to that of solder joint at 25 °C. Temperature dominates crack propagation path of solder joint during vibration test. Crack propagation path is changed from the area between intermetallic compound (IMC) layer and Cu pad to the bulk solder with temperature increase.     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

A single-bit sampling demodulator for biomedical implants

A phase-shift keying (PSK) demodulator is demonstrated for the target application of low power and high data rate inductive links. The demodulator based on the single-bit sampling demodulation scheme is capable of operating in binary, quadrature, 8-, and 16-PSK mode. The prototype chip realized in 0.18-µm CMOS process can demodulate up to 1.25 MSymbol/s at 5-MHz carrier frequency. It occupies 240×310 µm² and consumes 140 µA from 1.2 V.     

Analysis and resolution of a thermally accelerated early life failure mechanism in a 40 V GaN FET

An early life failure mechanism was discovered on a 0.25-µm 40 V GaN FET technology. Through accelerated life testing (ALT), it was determined that the early life failure mechanism was thermally accelerated with a high activation energy, which means that it is not a concern a normal operating conditions up to the maximum rated junction temperature. Subsequent improvements to the process resulted in elimination of the early life failure mechanism. With the improved process, single-mode ALT lifetime distributions and excellent reliability performance down to low failure fractions were demonstrated.     

Dependence of the optoelectronic properties of selenium-hyperdoped silicon on the annealing temperature

Selenium-hyperdoped silicon was prepared by ion implantation at 100 eV to a dose of 6×10¹⁵ Se/cm², followed by furnace annealing at 500–900 °C for 30 min. A phase transition from amorphous to crystalline was observed for the sample annealed at 600 °C. Carrier density in the Se doping layer gradually increases with the annealing temperature and a high carrier/donor ratio of 7.5% was obtained at 900 °C. The effects of annealing temperature on the rectifying behavior and external quantum efficiency of n⁺p junctions formed on Se-hyperdoped silicon were also investigated. We found that 700 °C was the optimal annealing temperature for improving the crystallinity, below-bandgap absorption, junction rectification and external quantum efficiency of Se-doped samples.     

Reliability assessment on new reprogrammable non-volatile memory devices based on SiCr–O

The reliability of SiCr–O based reprogrammable non-volatile resistive memory devices is investigated. Superior data retention performances are confirmed with a lifetime of 10 k h at 245 °C. The activation energy is determined by experiments as 1.28 eV, projecting an intrinsic data retention lifetime of more than 100 years at 175 °C. An endurance life of a thousand program/erase cycles is achieved. The impact of dielectric in direct contact with the SiCr–O film, the layout of the device and the preconditioning step on endurance life are studied. Transmission electron microscopy cross-sections are made to understand the mechanism of the endurance failure. Electro-thermal simulations are performed to gain insight on the observed phenomena and to give directions for further improvements.     

Reliability of high voltage/high power L/S-band Hbt technology

This paper presents the qualification methodology and results of an InGaP HBT process industrialised by UMS to cover high power L and S band applications. The high level of robustness of the technology has been demonstrated with RF test up to 9 dB compression without any degradation. MTTF of 12 FIT/mm² of semiconductor at a junction temperature of 175 °C have been demonstrated based on more than 560,000 component hours. Also, following the activation period, an asymptotic decrease of the Beta is pointed out both at WLR and long term reliability test and modelled by a Black law. Activation energy between 0.52 and 0.75 eV and a Black factor between 1 and 2 was found. An original and complete failure analysis methodology including NIR emission microscopy, FIB and TEM analysis, have been used to characterised infant mortality for which the root cause is attributed to the propagation through the base–emitter junction of dislocation in the epitaxy. Activation energy of 0.58 eV was determined for this mechanism.