Reliability of Cu wire bonds in microelectronic packages

In this study the thermo-mechanical response of 25 μm Cu wire bonds in an LQFP-EPad (Low Profile Quad Flat-Exposed Pad) package was investigated by numerical and experimental means. The aim was to develop a methodology for fast evaluation of the packages, with focus on wire bond fatigue, by combining finite element analysis (FEA) and mechanical fatigue testing. The investigations included the following steps: (i) simulation of the warpage induced displacements in the encapsulated LQFP-176-Epad package due to temperature changes, (ii) reproducing the thermally induced stresses in the wire bond loops in an unmolded (non-encapsulated) LQFP package using an accelerated multiaxial mechanical fatigue testing set-up under the displacement amplitudes determined in case (i) and determination of the loading cycles to failure (N_f), (iii) FEA of the experiments performed in (ii) based on the boundary conditions determined in (i) to calculate the states of stress and strain in the wire bonds subjected to multiaxial mechanical cyclic loading. Our investigations confirm that thermal and mechanical cyclic loading results in occurrence of high plastic strains at the heat affected zone (HAZ) above the nail-head, which may lead to fatigue failure of the wire bonds in the packages. The lifetime of wire bonds show a proportional relation between the location and angle of the wire bond to the direction of loading. The calculated accumulated plastic strain in the HAZ was correlated to the experimentally determined N_f values based on the volume weighted averaging (VWA) approached and presented in a lifetime diagram (∆ d - N_f) for reliability assessment of Cu wire bonds. The described accelerated test method could be used as a rapid qualification test for the determination of the lifetimes of wire bonds at different positions on the chip as well as for related improvements of package design.     

Transparent and flexible amorphous InZnAlO films grown by roll-to-roll sputtering for acidic buffer-free flexible organic solar cells

We report on transparent and flexible amorphous In–Zn–Al–O (a-IZAO) films prepared by roll-to-roll (RTR) sputtering for use as anodes in acidic buffer free flexible organic solar cells (FOSCs). The presence of Zn and Al structural stabilizers in the In₂O₃ matrix produced a completely amorphous structure with the high optical transmittance of 89.25% and the low resistivity of 2.123 × 10⁻³ Ω-cm, as well as the high work function of 5.14 eV, making the a-IZAO films suitable for use as flexible anodes for FOSCs. In addition, the a-IZAO films showed no change in resistance (ΔR) during outer and inner bending fatigue tests due to their good mechanical flexibility. Relative to the power conversion efficiency (1.944%) of a PEDOT:PSS-based FOSCs, a FOSC fabricated by using an a-IZAO anode and without the use of acidic PEDOT:PSS buffer showed greater power conversion efficiency (2.509%), owing to the absence of interfacial reactions between the acidic PEDOT:PSS and the a-IZAO anode.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.     

Ultra-thin alumina layer encapsulation of bulk heterojunction organic photovoltaics for enhanced device lifetime

Successful organic photovoltaic (OPV) device fabrication is contingent on selecting an effective encapsulation barrier layer to preserve device functionality by inhibiting atmosphere-induced degradation. In this work, ultra-thin AlO_x layers are deposited by atomic layer deposition (ALD) to encapsulate pre-fabricated OPV devices. A summary of ALD recipe effects (temperature, cycling time, and number of cycles) on AlO_x film growth and device longevity is presented. First, AlO_x film growth on the hydrophobic OPV surface is shown to occur by a 3D island growth mechanism with distinct nucleation and cluster growth regions before coalescence of a complete encapsulation layer with a thickness ⩾7 nm by 500 cycles. Encapsulated device performance testing further demonstrates that reducing ALD processing temperature to 100 °C minimizes OPV phase segregation and surface oxidation loss mechanisms as evidenced by improved short circuit current and fill factor retention when compared with the conventional 140–150 °C range. Ultra-thin AlO_x encapsulation by ALD provides significant device lifetime enhancement (∼30% device efficiency after 2000 h of air exposure), which is well beyond other ALD-based encapsulation works reported in the literature. Furthermore, the interfacial bonding strength at the OPV–AlO_x interface is shown to play a crucial role in determining film failure mode and therefore, directly impacts ultimate device lifetime.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

Interfacial evolution and bond reliability in thermosonic Pd coated Cu wire bonding on aluminum metallization: Effect of palladium distribution

In this paper, the growth kinetics of Cu–Al intermetallic compounds formed during isothermal annealing of Pd–Cu wire bonds with different palladium distribution at 175 °C are investigated by electron microscopy and compared to bare Cu wire bonds. Transmission electron microscopy (TEM) was used to provide high resolution imaging of the Cu–Al IMCs in the as-bonded state and TEM-EDX used to analyze the concentrations of Pd at the bond interface in the as-bonded state. Cu–Al IMCs were found to grow thicker with increasing annealing duration. The growth kinetics of the Cu–Al IMCs were correlated with the diffusion process during thermal annealing. The IMC thickness for Pd–Cu wire bonds with Pd at the bond interface was found to be thinner as compared to that for Pd–Cu wire bonds with no Pd at the bond interface. Thus, the presence of palladium at the bond interface has slowed down the IMC growth. Nano-voids were found in the Pd–Cu wire bonds with Pd at the bond interface, but not in the Pd–Cu wire bonds with no Pd at the bond interface. The IMC growth rate for the Pd–Cu bonds with no Pd was found to be close to that for bare Cu for the initial annealing durations. Corresponding bond pull testing showed that Pd–Cu wire bonds containing Pd have best preserved the bond strength after 168 h aging at 175 °C due to the beneficial presence of Pd.     

Hole mobilities of thermally polymerized triaryldiamine derivatives and their application as hole-transport materials in organic light-emitting diodes (OLEDs)

This paper describes the synthesis of three triaryldiamine derivatives presenting two thermally polymerizable trifluorovinyl ether groups that can be polymerized through thermal curing to form perfluorocyclobutyl (PFCB) polymers. These PFCB polymers, studied using time-of-flight techniques for the first time, exhibited remarkable non-dispersive hole-transport properties, with values of μ_h of ca. 10^?4 cm² V^?1 s^?1. When we employed these thermally polymerized polymers as hole-transport layers (HTLs) in electroluminescence devices containing tris(8-hydroxyquinolate) aluminum (Alq₃) as the emission layer, we obtained high current densities (ca. 3400 mA cm^?2), impressive brightnesses (5 × 10⁴ cd m^?2), and high external quantum efficiencies (EQEs = 1.43%). These devices exhibited the same turn-on voltage, but higher EQEs, relative to those incorporating the vacuum-processed model compound N,N′-di(1-naphthyl)-N,N′-diphenylbenzidine (α-NPD) (EQE = 1.37%) as the HTL under the same device structure.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

A fundamental understanding of nickel oxide based resistive random access memory with high percentage of oxygen

In this paper, we report the fundamental properties of NiO_x based Resistive RAM (RRAM) devices with Al top electrode and Ni bottom electrode. The NiO_x deposition was performed in a relatively high oxygen environment. The initial J–V curves in positive and negative bias indicated symmetric behavior in spite of a significant difference in the vacuum work functions of Al and Ni. The capacitance–voltage characterizations indicated NiO_x to be a p-type semiconductor with acceptor doping density between 6 × 10¹⁸ cm^?3 and 5 × 10²⁰ cm^?3. Switching behavior was observed after electroforming the devices. The devices failed after multiple switching cycles by switching into a relatively low conductive state. The mechanism of failure was attributed to the formation of Al₂O₃ due to a slow oxidation of Al electrodes with repeated cycles.     

Effect of annealing on the microstructure and bonding interface properties of Ag–2Pd alloy wire

This study investigated the mechanical and electrical properties of Ag–2Pd wire after thermal annealing. The thermal stability of the tested wire was examined by separately imposing static annealing at 275 °C, 325 °C and 375 °C in a vacuum environment. It was found that annealing the Ag–2Pd wire at 275 °C promoted the formation of a fully annealed structure with equiaxed grains. Annealing Ag–2Pd wire had a shorter heat affect zone (HAZ) length than those of conventional wire, and offered outstanding mechanical properties. A long-term electrical test found Ag₃(Pd)Al and Ag₂(Pd)Al compounds between the Ag–Pd ball and Al pad. These results confirmed the high-reliability properties of annealed Ag–2Pd wires for the wire bonding process.     

A detailed comparative study on the main electrical parameters of Au/n-Si and Au/PVA:Zn/n-Si Schottky barrier diodes

We have fabricated Au/n-Si and Au/PVA:Zn/n-Si Schottky barrier diodes (SBDs) to investigate the effect of organic interfacial layer on the main electrical characteristics. Zn doped poly(vinyl alcohol) (PVA:Zn) was successfully deposited on n-Si substrate by using the electrospinning system and surface morphology of PVA:Zn was presented by SEM images. The current–voltage (I–V) characteristics of these SBDs have been investigated at room temperature. The experimental results show that interfacial layer enhances the device performance in terms of ideality factor (n), zero-bias barrier height (Φ_B0), series resistance (R_s), and shunt resistance (R_sh) with values of 1.38, 0.75 eV, 97.64 Ω, and 203 MΩ whereas those of Au/n-Si SBD are found as 1.65, 0.62 eV, 164.15 Ω and 0.597 MΩ, respectively. Also, this interfacial layer at metal/semiconductor (M/S) interface leads to a decrease in the magnitude of leakage current and density of interface states (N_ss). The values of N_ss range from 1.36×10¹² at E_c—0.569 eV to 1.35×10¹³ eV^?1 cm^?2 at E_c—0.387 eV for Au/PVA:Zn/n-Si SBD and 3.34×10¹² at E_c—0.560 eV to 1.35×10¹³ eV^?1 cm^?2 at E_c—0.424 eV for Au/n-Si SBD. The analysis of experimental results reveals that the existence of PVA:Zn interfacial layer improves the performance of such devices.     

Fast power cycling protocols implemented in an automated test bench dedicated to IGBT module ageing

This paper presents fast test protocols for ageing IGBT modules in power cycling conditions, and a monitoring device that tracks the on-state voltage V_CE and junction temperature T_J of IGBTs during ageing test operations. This device is implemented in an ageing test bench described in previous papers, but which has since been modified to perform fast power cycling tests.The fast test protocols described here use the thermal variations imposed on IGBT modules by a test bench operating under Pulse Width Modulation conditions. This test bench reaches the maximal values of power cycling frequencies attainable with a given module packaging in order to optimize test duration.The measurement device monitors V_CE throughout the ageing test that is needed to detect possible degradations of wire bonds and/or emitter metallization. This requires identifying small V_CE variations (a few dozen mV). In addition, the thermal swing amplitude of power cycling must be adjusted to achieve a given ageing protocol. This requires measuring junction temperature evolution on a power cycle, which is carried out by means of V_CE measurement at a low current level (100 mA).Experimental results demonstrate the flexibility of this test bench with respect to various power cycling conditions, as well as the feasibility of the proposed on-line monitoring methods.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Optical and electrical characteristics of 17 keV X-rays exposed TiO2 films and Ag/TiO2/p-Si MOS device

This work presents the effect of varied doses of X-rays radiation on the Ag/TiO₂/p-Si MOS device. The device functionality was observed to depend strongly on the formation of an interfacial layer composed of SiO_x and TiO_y, which was confirmed by the spectroscopic ellipsometry. The XRD patterns showed that the as prepared TiO₂ films had an anatase phase and its exposure to varied doses of 17 keV X-rays resulted in the formation of minute rutile phase. In the X-rays exposed films, reduced Ti³⁺ state was not observed; however a fraction of Ti–O bonds disassociated and little oxygen vacancies were created. It was observed that the device performance was mainly influenced by the nature and composition of the interfacial layer formed at the TiO₂/Si interface. The spectroscopic ellipsometry was used to determine the refractive indices of the interfacial layer, which was 2.80 at λ=633 nm lying in between that of Si (3.87) and TiO₂ (2.11). The dc and frequency dependent electrical measurements showed that the interface defects (traps) were for both types of charge carriers. The presence of SiO_x was responsible for the creation of positive charge traps. The interface trap density and relaxation time (τ) were determined and analyzed by dc and frequency dependent (100 Hz–1 MHz) ac-electrical measurements. The appearance of peak in G/ω vs log (f) confirmed the presence of interface traps. The interface traps initially increased up to exposure of 10 kGy and then decreased at high dose due to compensation by the positive charge traps in SiO_x part of the interface layer. It was observed that large number of interface defects was active at low frequencies and reduced to a limiting value at high frequency. The values of relaxation time, τ ranged from 4.3±0.02×10⁻⁴ s at 0 V and 7.6±0.2×10⁻⁵ s at −1.0 V.     

Epitaxial growth of nonpolar GaN films on r-plane sapphire substrates by pulsed laser deposition

Single-crystalline nonpolar GaN epitaxial films have been successfully grown on r-plane sapphire (Al₂O₃) substrates by pulsed laser deposition (PLD) with an in-plane epitaxial relationship of GaN[1-100]//Al₂O₃[11-20]. The properties of the ~500 nm-thick nonpolar GaN epitaxial films grown at temperatures ranging from 450 to 880 °C are studied in detail. It is revealed that the surface morphology, the crystalline quality, and the interfacial property of as-grown ~500 nm-thick nonpolar GaN epitaxial films are firstly improved and then decreased with the growth temperature changing from 450 to 880 °C. It shows an optimized result at the growth temperature of 850 °C, and the ~500 nm-thick nonpolar GaN epitaxial films grown at 850 °C show very smooth surface with a root-mean-square surface roughness of 5.5 nm and the best crystalline quality with the full-width at half-maximum values of X-ray rocking curves for GaN(11-20) and GaN(10-11) of 0.8° and 0.9°, respectively. Additionally, there is a 1.7 nm-thick interfacial layer existing between GaN epitaxial films and r-plane sapphire substrates. This work offers an effective approach for achieving single-crystalline nonpolar GaN epitaxial films for the fabrication of nonpolar GaN-based devices.     

Paramagnetic Ge dangling bond type defects at (1 0 0)Si1−xGex/SiO2 interfaces (Invited Paper)

The work addresses the occurrence of Ge dangling bond type point defects at Ge_xSi_1?x/insulator interfaces as evidenced by conventional electron spin resonance (ESR) spectroscopy. Using multifrequency ESR, we report on the observation and characterization of a first nontrigonal Ge dangling bond (DB)-type interface defect in SiO₂/(1 0 0)Ge_xSi_1?x/SiO₂/(1 0 0)Si heterostructures (0.27 ? x ? 0.93) manufactured by the condensation technique, a selective oxidation method enabling Ge enrichment of a buried epitaxial Si-rich SiGe layer. The center, exhibiting monoclinic-I (C_2v) symmetry is observed in highest densities of ～7 × 10¹² cm^?2 of Ge_xSi_1?x/SiO₂ interface for x ～ 0.7, to disappear for x outside the ]0.45–0.87[ interval, with remarkably no copresence of Si P_b-type centers. Neither are trigonal Ge DB centers observed, enabling unequivocal spectral analysis. Initial study of the defect passivation under annealing in molecular H₂ has been carried out. On the basis of all data the defect is depicted as a Ge P_b1-type center, i.e., distinct from a trigonal basic Ge P_b(0)-type center (Ge₃Ge). The modalities of the defect’s occurrence as unique interface mismatch healing defect is discussed, which may widen our understanding of interfacial DB centers in general.     

Transient photovoltage and dark current analysis on enhanced open-circuit voltage of polymer solar cells with hole blocking TiO2 nanoparticle interfacial layer

The open-circuit voltage of bulk heterojunction polymer solar cells utilizing 1,8-diiodooctane (DIO) as a processing additive was greatly improved by using an organic layer coated TiO₂ nanoparticle interfacial layer inserted between the active layer and the Al electrode. The transient photovoltage measurement revealed that there was significant non-geminate recombination at the DIO-processed active layer/Al electrode interface. Reduced open-circuit voltage (V_OC) of the photovoltaic devices and high water contact angle of the DIO-processed active layer showed that the DIO-processed active layer has an undesirable surface composition for the electron collection. The organic layer coated TiO₂ nanoparticle interfacial layer effectively prevented the non-geminate recombination at the active layer/Al interface. As a result, we were able to significantly improve the V_OC and power conversion efficiency from 0.46 V and 2.13% to 0.62 V and 3.95%, respectively.     

Modular sensor chip design for package stress evaluation and reliability characterisation

A modular test chip comprising an array of 2 mm square modules has been designed and fabricated. The maximum chip size can be up to 10 mm square, i.e. a 5 × 5 array of modules. The motivation behind the test chip is primarily the need to address reliability concerns in the use of copper wire bonding. It is known that the move to replace gold wire bonding with copper, driven primarily by the escalating price of gold, leads to reliability challenges at the interfaces between the wire bonds, the bond pads and the mould compound. Its function is to address. The chip comprises daisy chain structures to monitor changes of wire bond resistance and leakage current, large and small area stress sensors to measure stress on the chip associated with die attach and moulding, and comb and triple track sensors to study corrosion and moisture penetration related to mould compound.     

Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy₂O₃ capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (J_G) reduction; (2) adding a cap has no significant impact on T_inv(<1 Å), while up to ～5 and 2 Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively, (3) the largest J_G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in J_G and mobility but with 500 mV smaller V_T; (4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; (5) excellent process control and reliability behavior (V_T instability by a.c. pulsed IV, PBTI and TDDB) is reported for both eWF tuning methods. They allow ΔeWF(n?p) values up to ～800 meV when combined with Ni–silicide FUSI phase engineering, promising for low-V_T CMOS.