Determination of the average channel temperature of GaN MOSHFETs under continuous wave and periodic-pulsed RF operational conditions

We present a method to determine the average device channel temperature of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOSHFETs) in the time domain under continuous wave (CW) and periodic-pulsed RF (radiation frequency) operational conditions. The temporal profiles of microwave output power densities of GaN MOSHFETs were measured at 2 GHz under such conditions and used for determination of the average channel temperature. The measurement technique in this work is also being utilized to determine the thermal time constant of the devices. Analytical temporal solutions of temperature profile in MOSHFETs are provided to support the method. The analytical solutions can also apply to generic field effect transistors (FETs) with an arbitrary form of time-dependent heat input at the top surface of the wafer. It is found that the average channel temperature of GaN MOSHFETs on a 300 μm sapphire substrate with the output power of 10 W/mm can be over 400 °C in the CW mode while the average channel temperature of GaN MOSHFETs on a SiC substrate with the same thickness only reaches 50 °C under the same condition. The highest average channel temperature in a pulsed RF mode will vary with respect to the duty cycle of the pulse and type of the substrate.     

Reliability of Cu nanoparticle joint for high temperature power electronics

Power cycle reliability of Cu nanoparticle joint has been studied for high temperature operation of power devices. Al₂O₃ heater chips and Cu–65 wt% Mo baseplates were joined by Cu nanoparticles and Sn–0.7Cu and power cycle tests of 65/200 °C and 65/250 °C were carried out on the joints. The Cu nanoparticles were prepared by reducing Cu carbonate in ethylene glycol with dodecanoic acid + dodecyl amine (C12) and decanoic acid and decyl amine (C10) as capping agents. A power cycle test of 65/200 °C did not inflict severe damage on the Cu nanoparticle joints so that there were not many cracks formed after 3000 cycles. Vertical cracks were formed in the C12 Cu nanoparticle joint after 3000 cycles of 65/250 °C test, however the maximum temperature during the power cycle test did not change at all because vertical cracks did not have an effect on preventing heat flow. On the contrary, lateral cracks were completely formed in the Sn–0.7Cu soldered joint after 200 cycles of 65/200 °C test and in the C10 Cu nanoparticle joint after 360 cycles of 65/250 °C test. In these experiments, the maximum temperatures were rapidly increased because heat conduction was prevented across the formed lateral cracks.     

Failure and stress analysis of through-aluminum-nitride-via substrates during thermal reliability tests for high power LED applications

The objective of this study is to evaluate the reliability of through-aluminum-nitride-via (TAV) substrate by comparing those experimental results with the finite element simulation associated with measurements of aluminum nitride (AlN) strength and the thermal deformation of Cu/AlN bi-material plate. Two reliability tests for high-power LED (Light emitting diode) applications are used in this study: one is a thermal shock test from − 40 °C to 125 °C, the other is a pressure cook test. Also, the strength of AlN material is measured by using three-point bending test and point load test. The reliability results show that TAV substrates with thicker Cu films have delamination and cracks after the thermal shock test, but there are no failure being found after the pressure cook test. The determined strengths of AlN material are 350 MPa and 650 MPa from three-point bending test and point load test, respectively. The measurement of thermal deformation shows that the bi-material plate has residual-stress change after the solder reflow process, also indicating that a linear finite element model with the stress-free temperature at 80 °C can reasonably represent the stress state of the thermal shock test from − 40 °C to 125 °C without considering Cu nonlinear effect. The further results of the finite element simulation associated with strength data of AlN material have successfully described those of the reliability test.     

Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

Thermal characterization of high power LED with ceramic particles filled thermal paste for effective heat dissipation

The next generation packaging materials are expected to possess high heat dissipation capability. Understanding the needs for betterment in the field of thermal management, the present study aims at investigating the package level analysis on a high power LED. In this study, commercially available thermal paste was heavily filled with ceramic particles of aluminium nitride (AlN) and boron nitride (BN) in order to enhance the heat dissipation of the device. Different particle sizes of AlN and BN fillers were incorporated homogenously into the thermal paste and applied as a thermal interface material (TIM) for an effective system level analysis employing thermal transient measurement. It was found that AlN TIM achieve less LED junction temperature by a difference of 2.20 °C compared to BN filled TIM. Furthermore, among D₅₀ = 1170 nm, 813 nm and 758 nm, the AlN at D₅₀ = 1170 nm was found to exhibit the lowest junction temperature of 38.49 °C and the lowest total thermal resistance of 11.33 K/W compared to the other two fillers.     

Power cycle reliability of Cu nanoparticle joints with mismatched coefficients of thermal expansion

The power cycle reliability of Cu nanoparticle joints between Al₂O₃ heater chips and different heat sinks (Cu-40 wt.%Mo, Al-45 wt.%SiC and pure Cu) was studied to explore the effect of varying the mismatch in the coefficient of thermal expansion (CTE) between the heater chip and the heat sink from 4.9 to 10.3 ppm/K. These joints were prepared under a hydrogen atmosphere by thermal treatment at 250, 300 and 350 °C using a pressure of 1 MPa, and all remained intact after 3000 cycles of 65/200 °C and 65/250 °C when the CTE mismatch was less than 7.3 ppm/K, despite vertical cracks forming in the sintered Cu. When the CTE mismatch was 10.3 ppm/K, the Cu nanoparticle joint created at 300 °C endured the power cycle tests, but the joint created at 250 °C broke by lateral cracks in the sintered Cu after 1000 cycles of 65/200 °C. The Cu nanoparticle joint created at 350 °C also broke by vertical cracks in the heater chip after 1000 cycles of 65/250 °C, suggesting that although sintered Cu can be strengthened to tolerate the stress by increasing the joint temperature, this eventually causes the weak and brittle chip to fracture through accumulated stress. The calculation results of stresses on the heater chip showed that the stress can be higher than the strength of Al₂O₃ when the CTE mismatch is 10.3 ppm/K and the Young's modulus of the sintered Cu is higher than 20 GPa, suggesting that the heater chip can be broken.     

Young's modulus of a sintered Cu joint and its influence on thermal stress

Al₂O₃ chips and pure Cu plates were joined by Cu nanoparticles at 250 °C and 350 °C, and the Young's moduli of the sintered Cu were evaluated by nanoindentation tests. The average Young's moduli were 52.7 ± 19.8 GPa and 76.5 ± 29.7 GPa at 250 °C and 350 °C, respectively, indicating that the sintered structures were strengthened at higher temperatures. The calculation results indicated that the joint at 350 °C has a high Young's modulus, but make the stress higher than the chip strength, resulting in breakage of the chip during 65/250 °C power cycling.     

High-lead flip chip bump cracking on the thin organic substrate in a module package

Flip chip bump cracking was observed after Si die attach reflow on the organic substrate of a module package. High-lead bump and eutectic SnPb cladding were used on Si die and the substrate sides, respectively. The reflow peak temperature was 260 °C for compatibility with passive components attach using lead-free solder. Flip chip bump cracking occurred at high-lead solder close to the die side. The cracking was eliminated by lowering the reflow peak temperature down to 225 °C. Main cause of the cracking at 260 °C reflow was attributed to the extensive Sn diffusion into high lead bump. This decreased the melting point of the high-lead solder around the die side, which in turn worsened the adhesion between solder and die due to the coexistence of solid and liquid. Diffusion length estimation showed both of the liquid- and solid-state diffusions of Sn. Crack gap in the solder bump was consistent with thermal expansion mismatch between Si die and organic substrate. The bump cracking was mitigated by use of 225 °C reflow, limiting Sn diffusion and providing a good integrity of high lead bumps on die side.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Effect of RF power and substrate temperature on the properties of boron and gallium co-doped ZnO films

Boron and gallium co-doped ZnO (BGZO) films were prepared by radio-frequency (RF) magnetron sputtering under different RF powers (50–250 W) at room temperature and 200 °C, respectively. The influence of sputtering power and substrate temperature on the structural, morphological, electrical and optical properties of BGZO films was investigated. The results indicated that all the films showed preferentially c-axis orientation and structure of hexagonal wurtzite. The grain size decreased at higher sputtering power above 150 W. The carrier concentration and optical band gap (E_g) increased with the increasing of RF sputtering power. At RF power of 150 W, the films showed higher mobility and lower resistivity. Average optical transmittance of all the BGZO films is greater than 85% in the visible wavelength and did not change obviously with the sputtering power or substrate temperature.     

Effects of substrate temperature on the degradation of RF sputtered NiO properties

Nickel oxide (NiO) film was grown on Si (100) substrate through RF sputtering of NiO target in Ar plasma at various temperatures ranging from room temperature (RT) to 300 °C. The structural study revealed (200) oriented NiO diffraction peak at RT and at 100 °C, however, by increasing the substrate temperature to 200 °C, intensity of (200) NiO diffraction peak was decreased. At higher temperature (300 °C), crystalline quality of NiO was significantly degraded and the film was decomposed into Ni. The EDS results confirmed an increase of Ni atomic percentage with increase of the substrate temperature. The surface morphology of NiO film at RT and at 100 °C displayed cubical like grains that were changed into elongated grains with further increase of the substrate temperature. The UV–vis reflectance measurements of NiO revealed a small decrease in its band gap by increasing the substrate temperature to 200 °C.     

Optimizing n-type contact design and chip size for high-performance indium gallium nitride/gallium nitride-based thin-film vertical light-emitting diode

The effects of the n-contact design and chip size on the electrical, optical and thermal characteristics of thin-film vertical light-emitting diodes (VLEDs) were investigated to optimize GaN-based LED performance for solid-state lighting applications. For the small (chip size: 1000×1000 µm²) and large (1450×1450 µm²) VLEDs, the forward bias voltages are decreased from 3.22 to 3.12 V at 350 mA and from 3.44 to 3.16 V at 700  mA, respectively, as the number of n-contact via holes is increased. The small LEDs give maximum output powers of 651.0–675.4 mW at a drive current of 350 mA, while the large VLEDs show the light output powers in the range 1356.7–1380.2 mW, 700 mA, With increasing drive current, the small chips go through more severe degradation in the wall-plug efficiency than the large chips. The small chips give the junction temperatures in the range 51.1–57.2 °C at 350  mA, while the large chips show the junction temperatures of 83.1–93.0 °C at 700  mA, The small LED chips exhibit lower junction temperatures when equipped with more n-contact via holes.     

Thermal analysis of active layer in organic thin-film transistors

This paper reports on the direct thermal observation of the pentacene – based organic thin-film transistors (OTFTs) under the real operating conditions. Liquid crystal (LC) spreading method was utilized for the thermal investigation of an active layer of the OTFT package. Temperature variation in the OTFT package was recorded for the different input power and significant heat generation was observed in the confined active layer. Detailed thermal performance of the OTFT package was projected using a Computational Fluid Dynamics (CFD) method as well. It was shown that the driving of the OTFT package with the drain voltage of ?15 V resulted in the active layer temperature of about 53.2 °C. The result indicates that the device design with effective thermal dissipation is imperative for reliable operation of the OTFT package.     

Phase-change immersion cooling high power light emitting diodes and heat transfer improvement

A new cooling method of ethanol direct-contact phase-change immersion cooling was proposed in the thermal management of high power light emitting diodes (LED) and the feasibility of this cooling method was investigated. The heat generated by LED was measured firstly using two types of power systems: DC power and LED driver. Then the heat dissipation performance was evaluated under different experimental conditions. The results indicate that startup process of the cooling system is quick and only 450 s is needed to reach steady-state under heat load of 42.78 W. The minimum thermal resistance of 1.233 °C/W is obtained when liquid filling ratio is 33.14%. The junction temperature of LED under different absolute pressures is much lower than the limited value of 120 °C. Baffle with total height of 140 mm, bottom space height of 20 mm and distance away from substrate surface of LED of 8 mm improves heat transfer performance best due to ethanol self-circulating in the cooling receiver. Overall, the ethanol phase-change immersion cooling is an effective way to make sure high power LED work reliably and high efficiently.     

Process optimization of RTA on the characteristics of ITO-coated GaN-based LEDs

We present a detailed study on the optimization of rapid thermal annealing (RTA) on GaN-based light emitting diodes (LEDs). 14 mil × 28 mil GaN-based LED chips are fabricated with indium tin oxide (ITO) layer treated by RTA under various temperatures and times. Through the optical and electrical property analyses of ITO film, it is found that the transmittance and sheet resistance are improved after RTA process due to the better ITO crystallization and bigger grain size, compared with ITO treated by conventional furnace annealing. By employing electroluminescence measurement for the LED chips with RTA treatment, the forward voltage is found to be low as a result of low sheet resistance and contact resistance, and light output power (LOP) is high due to high ITO transmittance and good current density uniformity. Under RTA temperature of 550 °C and time of 3 min, the optimized LOP and forward voltage at 60 mA injection current are 71.2 mW and 2.97 V, respectively. Moreover, the reliability of the chips with RTA is better than those with furnace annealing.     

Low-temperature low-pressure die attach with hybrid silver particle paste

New types of die attach pastes comprising micron-sized Ag particles hybridized with submicron-sized Ag particles were considered as lead-free die attach materials for SiC power semiconductors. Micron-sized Ag particles in alcohol solvent were prepared by mixing the die attach paste with submicron-sized Ag particles. The alcohol vaporizes completely during sintering and no residue exists in the bonding layer. The Ag layer has a uniform porous structure. The electrical resistivity of the printed tracks decreases below 1 × 10^?5 Ω cm when sintered above 200 °C. When sintered at 200 °C for 30 min, the average resistivity reaches 5 × 10^?6 Ω cm, which is slightly higher than the value obtained by using Ag nanoparticle paste. A SiC die was successfully bonded to a direct bonded copper substrate and the die-shear strength gradually increases with the increase in bonding temperature up to 300 °C. The Ag die attach bond layer was stable against thermal cycles between ?40 °C and 300 °C.     

Effects of oxidation on reliability of screen-printed silver circuits for radio frequency applications

High reliability has become one of the crucial requirements for portable electronic devices, due to the high dependence of their radio frequency (RF) characteristics on the end-user's surroundings. The RF characteristics of screen-printed silver (Ag) circuits were investigated after a steady-state temperature and humidity storage test. A conductive paste containing Ag nanoparticles was screen-printed onto a silicon (Si) substrate and then sintered at 250 °C for 30 min in air. The printed Ag circuits were placed in a chamber at 85 °C/85% relative humidity (RH) for various durations: 100, 300, 500, 1000 h. The microstructural evolution and thickness profiles of the Ag circuits were observed with field emission scanning electron microscopy and α-step, respectively. The oxidation of the printed Ag circuit surface was analyzed with Auger electron spectroscopy. A network analyzer and Cascade's probe system in the frequency range of 40 MHz to 40 GHz were employed to measure the scattering parameters of the Ag circuits. The experimental results showed that the insertion losses at higher frequencies increased with increasing durations of exposure to the 85 °C/85% RH environment, due to the thicker specific layer for oxidation on the circuit surfaces. The oxide layer was the dominant factor affecting the RF characteristics of the screen-printed Ag thin circuits. Therefore, it is essential to control the oxidation of printed circuits for versatile RF applications.     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.     

End of life and acceleration modelling for power diodes under high temperature reverse bias stress

This work is motivated by the growing importance of lifetime modelling in power electronics. Strongly accelerated High Temperature Reverse Bias (HTRB) testing of power diodes at different stress conditions is performed until alterations and fatigue mechanisms become evident. Two categories of effects can be separated: Drifting breakdown voltage and hard failures with complete loss of blocking capability. Nevertheless the overall stress duration needed to provoke destructive failures is very high with test durations > 2500 h even at almost 230 °C and 100% rated voltage. For both mechanisms the temperature and voltage acceleration is evaluated. Especially temperature acceleration is significant in the regime of testing between 200 °C and 230 °C and an activation energy E_a in the regime > 1 eV can be deduced which is higher compared to values commonly reported in the literature. Failure analysis shows that both package and also chip related effects could contribute to the observed hard failures in HTRB stress under extreme conditions.     

Defect and microstructural evolution in thermally cycled Cu through-silicon vias

In this study, the effect of thermal cycling on defect generation, microstructure, and RF signal integrity of blind Cu through-silicon vias (TSVs) were investigated. Three different thermal cycling profiles were used; each differentiated by their peak cycling temperature (100 °C, 150 °C, 200 °C) and the time needed to complete one cycle (cycle time). The study was performed on two Cu TSV wafer sample types; one containing large processing-induced voids (voided sample), the other without (non-voided sample). It was found that the RF signal return loss |S₁₁| of the Cu TSVs increased upon thermal cycling for both the voided and the non-voided sample types. This was attributed to the increase in the void area due to the formation of new voids, rather than the growth of preexisting voids. On the other hand, the grain orientation and grain sizes of the Cu TSVs were found to be unaffected by all studied thermal cycling conditions and sample types.