A novel algorithm for high-throughput programming of multilevel flash memories

This paper presents a new method to program multilevel (ML) flash memories that combines ramped-gate programming with minimum verification of the sense transistor threshold voltage, in order to achieve high program throughput, i.e., number of bits programmed per second. Such a method is studied by means of extensive measurements on production quality test chips and is found able to allow a program throughput about three times as large as the state of the art presented in the literature. Furthermore, it is found adequate for 3-bit-per-cell multilevel schemes, while for the extension to the 4-bit-per-cell case the use of error correcting codes cannot be avoided.     

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NORtype four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm² die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed     

Device characteristics of 0.35 μm P-channel DINOR flash memoryusing band-to-band tunneling-induced hot electron (BBHE)programming

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-μm-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 μs/512 byte) and a low current consumption of less than 250 μA were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10⁶ program/erase cycles, and window narrowing and G_m degradation were found to be very small even after 10⁶ cycles. It is thought that the BBHE injection point contributes to the G _m stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories     

A dual-page programming scheme for high-speed multigigabit-scaleNAND flash memories

To realize a low-cost and high-speed programming NAND flash memory, a new programming scheme, a “dual-page programming scheme,” has been proposed. This architecture drastically increases the program throughput without circuit area overhead. In the proposed scheme, two memory cells are programmed at the same time using only one page buffer. Therefore, the page size, i.e., the number of memory cells programmed simultaneously, is doubled and the program speed is improved. As the number of page buffers required in the proposed scheme is the same as that in the conventional one, there is no circuit area increase. This novel operation is made possible by using a bitline as a dynamic latch to temporarily store the program data. As a result, the programming is accelerated by 73% in a 1-Gb generation and 62% in a 4-Gb generation, 18.2-MB/s 1-Gb or 30.7-MB/s 4-Gb NAND flash memory can be realized with this new architecture     

A multipage cell architecture for high-speed programming multilevelNAND flash memories

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V_th of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 μs/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized     

A PWM analog memory programming circuit for floating-gate MOSFETswith 75-μs programming time and 11-bit updating resolution

This paper describes a programming circuit for analog memory using pulsewidth modulation (PWM) signals and the circuit performance obtained from measurements using a floating-gate EEPROM device. This programming circuit attains both high programming speed and high precision. We fabricated the programming circuit using standard 0.6-μm CMOS technology and constructed an analog memory using the programming circuit and a floating-gate MOSFET. The measurement results indicate that the analog memory attains a programming time of 75 μs, an updating resolution of 11 bit, and a memory setting precision of 6.5 bit. This programming circuit can be used for intelligent information processing hardware such as self-learning VLSI neural networks as well as multilevel flash memory     

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm² die size and a 1.1 μm² effective cell size     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

Novel self-limiting high-speed program scheme of p-channel DINORflash memory with n-channel select transistors

This paper describes a novel self-limiting high-speed program scheme of the p-channel DINOR (D_I_vided bit line N_O_R_) flash memory utilizing n-channel select transistors. This scheme makes it possible to maintain the high programming throughput of the p-channel DINOR even for future lower-voltage operation. Using this scheme, programming stops automatically at the desired threshold voltage state without any conventional verify operations. Moreover, the only structural change from the conventional p-channel DINOR is the change of the impurity type of the select transistors, and the only operational change is the addition of a very short negative voltage pulse of 0.1 μs to each programming gate pulse. This shortness of the additional pulse hardly degrades the programming speed at all. This novel scheme is expected to become a key technology for the realization of future, high-performance, lower-supply-voltage p-channel DINOR flash memories     

An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.     

Trading-off programming speed and current absorption in flashmemories with the ramped-gate programming technique

This work studies the trade-off between programming speed and current absorption in flash EEPROM memories that can be achieved using a ramped-gate programming (RGP) method. The writing parallelism as a function of the programming speed is discussed and it is shown how the flexibility of the RGP scheme can be effectively used to meet very different programming requirements. In particular, the results of this paper address two significant applications: a highly parallel (2 K cells) soft-programming procedure able to remarkably tighten erased V _T distribution and a multilevel, high bandwidth (1 Mbytes/s) programming operation. For both applications, the most relevant issues for a practical use are discussed, such as the choice of drain and substrate voltages in relation to current absorption, the statistical distribution of programmed threshold voltages, and the endurance characteristics     

A 144-Mb, eight-level NAND flash memory with optimized pulsewidthprogramming

We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-μm CMOS process, resulting in a 104.2-mm² die size and a 1.05-μm² effective cell size     

A 256-Mb multilevel flash memory with 2-MB/s program rate for massstorage applications

A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm² die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V_th. The effect of adjacent memory cell's V_th is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V_th. In the -5-75°C range, memory threshold V_th deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector     

A stable programming pulse generator for single power supply flashmemories

A stable programming pulse generator has been developed for single power supply, high-speed programming, and low-power flash memories. The newly developed delay circuit operates by amplifying the difference between the reference voltage and the capacitor voltage raised by the charging current which is proportional to the reference voltage. Linearity between the capacitor voltage swing and the driving current enables us to make the delay circuit supply voltage-, temperature-, and process-tolerant. Thus, the proposed delay circuit stably controls a programming pulse width through all operational ranges of supply voltage and temperature. The output frequency of the newly developed oscillator is inversely proportional to the supply voltage. This oscillator stably drives charge pump circuits which generate high programming voltages on chip since dependence of charge pump characteristics on frequency and supply voltage can be cancelled. As a result, the programming pulse generator including the delay circuit and the oscillator has reduced the total programming time under the slowest condition, i.e., high temperature and low voltage condition, by 30% and the power consumption under the fastest condition, i.e., low temperature and high voltage condition, by 20%, for a 3.3 V-only flash memory     

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byteeffective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm² and an effective cell size of 1.1 μm²     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

Performance and reliability improvement of flash device by a novel programming method

The operating methods of flash memory device are worth studying due to the reliability issue. A novel programming method based on a new current mechanism is developed in this work to improve the performance and reliability of flash memory. Experimental results show that this novel programming method with higher gate current injection efficiency not only increases the operating speed but also improves the reliability. This reliability improvement can be attributed to the reduction of oxide-trap-charge generation and threshold-voltage shift.     

Erratic cell behavior in channel hot electron programming of NOR flash memories

This paper describes for the first time an erratic behavior found in NOR array cells of flash memories after cycling when programming is performed by channel hot electron injection. The effects of different program conditions (i.e., drain and bulk bias, as well as program speed) on such an erratic behavior are discussed and a possible explanation is given. Implications in terms of memory reliability are discussed, in particular for multilevel applications.