The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

Comparison of GaAs device approaches for ultrahigh-speed VLSI

The superior electronic properties of gallium arsenide and related III-V compound semiconductors, as compared with silicon, have made them of great interest for ultrahigh-speed logic applications. Many ingenious device structures have been proposed or demonstrated for utilizing the advantageous electron dynamics of GsAs to achieve ultralow propagation delay and/or ultralow power-delay product (dynamic switching energy) logic circuits. The intent of this paper is to give an overview of some of these GaAs device approaches, including their principal, attractions, expected performance levels, etc. (Much more detailed analyses of some of these structures are presented in other papers in this issue.) This overview is extended to a comparison of the relative merits of these GaAs device approaches vis-à-vis their applicability for achieving ultra high-speed logic of large-scale integration (LSI) or very large-scale integration (VLSI) levels of complexity (as opposed to simpler SSI/MSI applications).     

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward     

Power rail logic: a low power logic style for digital GaAs circuits

This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits. Multiplexors, latches, flip-flops, and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-b barrel shifters designed in DCFL and in PRL was successfully fabricated and tested. Test results are given for both circuits     

An ultrahigh-speed GaAs MESFET operational amplifier

A wide-bandwidth GaAs MESFET operational amplifier is reported, with a 65-dB DC gain and a 20-GHz gain-bandwidth product at 500 MHz. The circuit uses a variety of local feedback techniques to enhance the overall gain. The use of an undoped GaAs buffer, grown at a relatively low temperature (≈300°C), eliminates backgating and light sensitivity. The circuit was fabricated in an 80-GHz f_T MESFET process, with 0.2-μm electron-beam defined gates. The high levels of 1/f noise, MESFET frequency-dependent output conductance, and large offset voltage standard deviation limit the application of the circuit to moderate precision applications     

Integrated injection logic for VLSI

This study shows that reducing the basewidth of I²L structures improves the intrinsic βuibut improvements in the extrinsic βueand the delay times at low-current levels are less significant while high-current performance is degraded. Narrowing the epi region improves both βuiand βueand the delay times at high currents, but degrades injection region efficiency λ, and delay times at low currents.     

Substrate integrated waveguides optimized for ultrahigh-speed digital interconnects

This paper reports an experimental and computational study of substrate integrated waveguides (SIWs) optimized for use as ultrahigh-speed bandpass waveguiding digital interconnects. The novelty of this study resides in our successful design, fabrication, and testing of low-loss SIWs that achieve 100% relative bandwidths via optimal excitation of the dominant TE/sub 10/ mode and avoidance of the excitation of the TE/sub 20/ mode. Furthermore, our optimal structures maintain their 100% relative bandwidth while transmitting around 45/spl deg/ and 90/spl deg/ bends, and achieve measured crosstalk of better than -30 dB over the entire passband. We consider SIWs operating at center frequencies of 50 GHz, accommodating in principle data rates of greater than 50 Gb/s. These SIWs are 35% narrower in the transverse direction and provide a 20% larger relative bandwidth than our previously reported electromagnetic bandgap waveguiding digital interconnects. Since existing circuit-board technology permits dimensional reductions of the SIWs by yet another factor of 4:1 relative to the ones discussed here, bandpass operation at center frequencies approaching 200 GHz with data rates of 200 Gb/s are feasible. These data rates meet or exceed those expected eventually for proposed silicon photonic technologies.     

Temperature stability of ultrahigh-speed GaAs JFET ICs

Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100°C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100°C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs     

VLSI for digital television

The paper provides an overview of the current status in the industry of digitized television including techniques used and their limitations, technological concerns and design methodologies needed to achieve the goals for highly integrated systems. A multiresolution scalable generic HDTV codec based on subband coding is presented, proving the feasibility of VLSI for true HDTV frequency. In addition, a VLSI design methodology is proposed based on programmable processor macrofunctions optimized for the huge amount of data to be processed. The goal was to integrate general VLSI implementation aspects in a specific digital codec system to validate the design methodology for high speed multimedia applications. Digital TV functions can be optimized for encoding and decoding in the same conceptual process and be implemented in silicon in a mole dedicated way using a kind of automated custom design approach allowing enough flexibility     

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.     

Threshold voltage adjustable GaAs FET for VLSI

The concept of externally adjusting the threshold voltage of a quasiMISFET by means of a second specially structured gate located underneath the channel is proposed and has been verified experimentally. The new concept should allow fabrication of III-V compound semiconductor integrated circuits with relaxed threshold voltage uniformity requirements. Using this transistor the radiation of the direct-coupled FET logic (DCFL) is possible.<>     

VLSI logic design with logic programming and knowledge-basetechnology

An approach to VLSI logic design using partial and general structural specifications in addition to behavioral specifications is developed. This approach requires a new style of programming technique, especially if a universal solution procedure for all types of architectures is needed. Knowledge of the design process involves unification of the heterogeneous (i.e. behavior and structure) information between a system and its parts, as well as representation of functional modules in order to ensure their reusability in an efficient manner. Following these strategies, a logic synthesis expert system, ProLogic, is developed, and the system is evaluated using MPU-type VLSIs. It is found that the universal connecting procedure for any compound functional module that unifies the behavioral and structural specifications between a total module and its parts improves logic design efficiency by a factor of 2 and that logic programming, object-oriented frames, and rule bases implemented in ProLogic improve software productivity by a factor of 5     

VLSI for analog/digital communications

Present trends and future prospects are discussed, emphasizing the prospects for fuller VLSI integration of low-power digital radio, for applications such as in-building wireless radio receivers. The main concern is with the front end of the receiver, including continuous-time analog and sampled analog VLSI filtering, and technologies that can mix analog and digital on the same chip. Prospects for the use of bipolar complementary metal-oxide semiconductor (BiCMOS) technology in communications are examined. Continuous-time monolithic filtering is discussed. As an example of a central receiver/transmitter component that one would like to integrate monolithically, the frequency synthesizer is considered     

The evolution of digital electronics towards VLSI

Technological trends are extrapolated to the end of this century. Problems of utilizing high levels of integration are noted, and the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems. A physical model and some more speculative system assumptions are used to estimate the performance of the systems. The physical characteristics forecast for the system are summarized.     

0.15 mu m GaAs MESFETs applied to ultrahigh-speed static frequency dividers

0.15 mu m gate-length FETs fabricated by SAINT using photo lithography are applied to ultrahigh-speed static frequency dividers. Short channel effects are suppressed by a buried p-layer and shallow active layers formed by low energy implantations and rapid thermal annealing. The maximum cutoff frequency of the 0.15 mu m gate-length FETs was 80.6 GHz. The maximum toggle frequency of the LSCFL one-quarter frequency divider is 26.8 GHz with a power dissipation of 263 mW.<>     

The evolution of digital electronics towards VLSI

Technological trends are extrapolated to the end of this century. Problems of utilizing high levels of integration are noted, and the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems. A physical model and some more speculative system assumptions are used to estimate the performance of the systems. The physical characteristics forecast for the system are summarized.     

Fuzzy logic approach to VLSI placement

A contemporary definition of VLSI placement problem is characterized by multiple objectives. These objectives are: timing, chip area, interconnection length and possibly others. In this paper, fuzzy logic has been used to facilitate multiobjective decision-making in placement for standard cell design style. A placement process has been defined in terms of linguistic variables, linguistic values and membership functions. Various objectives have been related by hierarchical fuzzy logic rules implemented as object-oriented programming objects. It is demonstrated that a designed fuzzy logic system is flexible in selecting goals and considering tradeoffs. Details of implementation, experimental results and comparisons with other systems are provided     

CORDIC-based VLSI architectures for digital signal processing

The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms