A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.     

Impact of surrounding gate transistor (SGT) for ultra-high-densityLSI's

A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed     

Characterization of parasitic transistors to evaluate CMOS processuniformity

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed and their application to process control examined. These transistors are characterized and their extracted parameters correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors are very sensitive to changes in the process that influence the performance of MOS transistors. As a result parasitic transistors can be used in conjunction with standard MOS devices and test structures to provide a more complete picture of CMOS process variation     

Metrology Challenges for Emerging Research Devices and Materials

As silicon complimentary metal-oxide-semiconductor (CMOS) technology approaches its limits, new device structures and computational paradigms will be required to replace and augment standard CMOS devices for ULSI circuits. These possible emerging technologies span the realm from transistors made from silicon nanowires to heteroepitaxial layers for spin transistors to devices made from nanoscale molecules. One theme that pervades these seemingly disparate emerging technologies is that the electronic properties of these nanodevices are extremely susceptible to small perturbations in structural and material properties such as dimension, structure, roughness, and defects. The extreme sensitivity of the electronic properties of these devices to their nanoscale physical properties defines a significant need for precise accurate metrology. This paper will describe some of the most critical metrology required to characterize materials and devices in the research and exploratory stage and how these requirements would potentially change if these research devices were to start into a technology development effort     

A fully complementary BiCMOS technology for 10 V mixed-signalcircuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization     

A versatile half-micron complementary BiCMOS technology formicroprocessor-based smart power applications

A modular, high density 0.5 μm Complementary BiCMOS technology with integrated high-voltage Lateral Diffused MOS (LDMOS) and conductivity modulated Lateral Insulated Gate Bipolar Transistor (LIGBT) structures designed for high performance, multi-functional integrated circuit applications is described. The advantages of VLSI processing and 0.5 μm compatible layout rules have been applied to the design and fabrication of the tight-pitch high-voltage devices without sacrificing the performance of 0.5 μm dual-poly (N+/P+) gate CMOS and complementary vertical bipolar transistors. Single chip integration of VLSI microprocessors with high-voltage and/or high-current input and output functions for “Smart Power” applications can be achieved using this technology     

Fully integrated voiceband codec in a standard digital CMOS technology

A 2.7-V complete voiceband codec with high-performance speech interfaces is presented. It includes a low-noise microphone preamplifier and loudspeaker/earpiece drivers. In the 4-kHz signal bandwidth, the ADC achieves a dynamic range of 80 dB and a full scale S/(THD + N) ratio of 71 dB, while the DAC performs 84 dB and 75 dB, respectively. These performances have been obtained in a pure digital low-cost CMOS process. The only components used are standard nMOS and pMOS transistors, parasitic vertical PNP bipolar transistors, unsalicided poly resistors, nonlinear poly-nwell capacitors, and a few small linear capacitors made with a sandwich of five metals and poly. The active area is 2.7 mm/sup 2/ in a 0.35-/spl mu/m, five metal levels, standard digital CMOS technology. Power dissipation is 12 mW. The cell can be easily migrated in more advanced processes with area reduction. A migration in a 0.18-/spl mu/m digital CMOS process has been achieved.     

SODS: a new CMOS differential-type structure

Differential-type structures to implement Boolean functions find very interesting applications in self-timed circuits. A novel structure of CMOS differential circuit called Switched Output Differential Structure (SODS) is presented in this paper. This structure has been designed modifying the LOAD circuitry of previously reported differential structures, gaining in terms of transistor-count and area. This cell has been implemented on a standard 1.5 μm technology and has served to assess the structures and compare it with previously reported differential structures. Experimental laboratory results, as well as electrical simulation, show improved timing and power performance, i.e., 470 MHz and 0.46 mW at 50 MHz, respectively, for the buffer-inverter operation, with Vdd=5 V     

4-2 compressor of fast booth multiplier for high-speed RISC processor

A 4-2 compressor for a fast booth multiplier is designed and optimized by two circuits configurations one is constructed of different but optimized XOR circuits with 44 transistors and a total transistor size W/L of 574. The other one is made of single to dual rail transmission gates (TGs) with 56 transistors and a total transistor size W/L of 467. The maximum propagation delay, the power consumption and the chip (layout) area of the two configuration 4-2 circuits are simulated with 0.3?μm and 0.2?μm CMOS process parameters. The results show that the delay and power consumption of circuits with 0.2?μm technology are smaller than those of circuits with 0.3?μm technology. Also, 4-2 circuits are synthesized. This is supported by 0.2?μm CMOS library and design compiler (DC) software (Tools) and compared with the proposed circuits of this research, the designed TG 4-2 compressor is faster and area smaller than that of synthesized one, so the designed TG 4-2 compressors can be optimized for high speed and small chip area applications when compared with the synthesized structures.     

Very low-voltage analog signal processing based on quasi-floating gate transistors

A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.     

Low-voltage low-power improved linearity CMOS active resistor circuits

A tutorial of CMOS active resistor circuits will be presented in this paper. The main advantages of the proposed implementations are the improved linearity, the small area consumption and the improved frequency response. In order to improve their linearity, improved performances linearization techniques will be proposed, with additional care for compensating the errors introduced by second-order effects. Design techniques for minimizing the silicon area consumption will be further presented and FGMOS (Floating Gate MOS) transistors will be used for this purpose. The frequency response of the circuits is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of an important part of their blocks. Additionally, small changing in each design allows to obtain negative controllable equivalent resistance circuits. The circuits are implemented in CMOS technology, SPICE simulations confirming the theoretical estimated results, showing small values of the linearity error (under 0.15% for the best design) for an extended input range and for a supply voltage equal with ±3 V. The proposed circuits respond to low-voltage low-power requirements, their design being adapted to the continuous degradation of the model quality associated with the evolution toward latest nanotechnologies.     

Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS

This paper describes how standard NMOS technology can be modified to provide CMOS devices [1]. This is done by creating p-channel transistors in an active polysilicon layer. This stacked transistors CMOS (ST-CMOS) technology may be considered as a step towards a three-dimensional (3-D) integration, which is a possible approach for increasing the IC's packing density. All of the steps in the process are standard but one: the laser annealing of processed wafers. A crucial step in this ST-CMOS process is the laser annealing of a multilayer structure: the technique of selective annealing has been developed and optimized.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Transconductance amplifier structures with very smalltransconductances: a comparative design approach

A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small G_m's (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-μm n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results     

Design of CMOS amplifiers with offset rejection using positive-feedback QFG transistors

Two novel complementary design techniques of very-low DC gain CMOS amplifiers are presented. They are based on two classical positive-feedback structures for gain enhancement, increasing the equivalent load resistance and the transconductance of the input differential pair respectively. Quasi-Floating Gate transistors have been employed for designing frequency-dependent structures that reduce strongly the amplifier gain in DC and at very low frequencies, allowing the conventional high gain at frequencies starting at a few Hz. These broadband features make the proposed design techniques suitable for applications where weak input signals with large DC offset voltages have to be handled, such as biomedical signal processing or direct conversion communication receivers. Both ideas have been applied to simple one stage OTAs that have been fabricated in a 0.5 μm n-well technology. Measurement results are provided for validating the proposed techniques.     

Stacked Transistors CMOS (ST-MOS), an NMOS Technology Modified to CMOS

This paper describes how standard NMOS technology can be modified to provide CMOS devices [1]. This is done by creating p-channel transistors in an active polysilicon layer. This stacked transistors CMOS (ST-CMOS) technology may be considered as a step towards a three -dimensional (3-D) integration, which is a possible approach for increasing the IC's packing density. All of the steps in the process are standard but one: the laser annealing of processed wafers. A crucial step in this ST-CMOS process is the laser annealing of a multilayer structure: the technique of selective annealing has been developed and optimized.     

Novel high-precision current-mode multiplier/divider

In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using this method. Proposed circuits have been simulated with SPICE simulator using 0.35 μm CMOS technology parameters. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. As a result, it can be considered as a useful building block for IC designer.     

Over rail-to-rail fully differential voltage-to-current converters for nm scale CMOS technology

The converters presented in this paper are based on long channel complementary MOS transistors, instead of the commonly used differential amplifiers or differential transistor pairs which are difficult to implement in low voltage, nm scale CMOS technology. Nonlinearities of drain currents can be cancelled in the fully differential structure. As a result, the low power, nanometre standard digital CMOS technology converters are obtained. Layout examples are designed in 65 nm TSMC technology. Post-layout simulations show that the range of input voltage over rail-to-rail is achieved with very good linearity and reduced harmonic distortion.     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability

Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential     

Analogue switch for very low-voltage applications

A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS technology is presented. The proposed switch is based on 'quasi-floating-gate' transistors and has a simple and compact structure. For illustrative purposes, two sample-and-hold circuits operating from a single supply voltage close to the threshold voltage of a transistor, and using the proposed technique, are presented. Experimental results obtained from prototypes in a 1.5 /spl mu/m CMOS technology are provided.