Area-Efficient Min-Sum Decoder Design for High-Rate Quasi-Cyclic Low-Density Parity-Check Codes in Magnetic Recording

We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-check (LDPC) code decoder. Our design method is geared to magnetic recording that demands high code rate and very high decoding throughput under stringent silicon cost constraints. The key to designing the decoder is to transform the conventional formulation of the min-sum decoding algorithm in such a way that we can readily develop a hardware architecture with several desirable features: 1) silicon area saving potential inherent in the min-sum algorithm for high-rate codes can be fully exploited; 2) the decoder circuit critical path may be greatly reduced; and 3) check node processing and variable node processing can operate concurrently. For the purpose of demonstration, we designed application-specific integrated circuit decoders for four rate-8/9 regular-(4, 36) QC-LDPC codes that contain 512-byte, 1024-byte, 2048-byte, and 4096-byte user data per codeword, respectively. Synthesis results show that our design method can meet the beyond-2 Gb/s throughput requirement in future magnetic recording at minimal silicon area cost.     

Improved regular and semi-random rate-compatible low-density parity-check codes with short block lengths

Powerful rate-compatible codes are essential for achieving high throughput in hybrid automatic repeat request (ARQ) systems for networks utilising packet data transmission. The paper focuses on the construction of efficient rate-compatible low-density parity-check (RC-LDPC) codes over a wide range of rates. Two LDPC code families are considered; namely, regular LDPC codes which are known for good performance and low error floor, and semi-random LDPC codes which offer performance similar to regular LDPC codes with the additional property of linear-time encoding. An algorithm for the design of punctured regular RC-LDPC codes that have low error floor is presented. Furthermore, systematic algorithms for the construction of semi-random RC-LDPC codes are proposed based on puncturing and extending. The performance of a type-ll hybrid ARQ system employing the proposed RC-LDPC codes is investigated. Compared with existing hybrid ARQ systems based on regular LDPC codes, the proposed ARQ system based on semi-random LDPC codes offers the advantages of linear-time encoding and higher throughput.     

Power optimised channel coding in wireless sensor networks using low-density parity-check codes

Energy consumption of low-density parity-check (LDPC) codes in different implementations is evaluated. Decoder's complexity is reduced by finite precision representation of messages, that is, quantised LDPC decoder, and replacement of function blocks with look-up tables. It is shown that the decoder's energy consumption increases exponentially with the number of quantisation bits. For the sake of low-power consumption, 3-bit magnitude and 1-sign bit representation for messages are used in the decoder. It is concluded that high-rate Gallager codes are as energy efficient as the Reed-Solomon codes, which till now have been the first choice for wireless sensor networks (WSNs). Finally, it is shown that using LDPC codes in WSNs can be justified even more by applying the idea of trading the transmitter power with the decoder energy consumption. By exploiting the trade-off inherent in iterative decoding, the network lifetime is increased up to four times with the 3-6 regular LDPC code. Hence, it is inferred that the LDPC codes are more efficient than the block and the convolutional codes.     

Low-density parity-check codes for volume holographic memory systems

We investigate the application of low-density parity-check (LDPC) codes in volume holographic memory (VHM) systems. We show that a carefully designed irregular LDPC code has a very good performance in VHM systems. We optimize high-rate LDPC codes for the nonuniform error pattern in holographic memories to reduce the bit error rate extensively. The prior knowledge of noise distribution is used for designing as well as decoding the LDPC codes. We show that these codes have a superior performance to that of Reed-Solomon (RS) codes and regular LDPC counterparts. Our simulation shows that we can increase the maximum storage capacity of holographic memories by more than 50 percent if we use irregular LDPC codes with soft-decision decoding instead of conventionally employed RS codes with hard-decision decoding. The performance of these LDPC codes is close to the information theoretic capacity.     

Efficient secure channel coding based on quasi-cyclic low-density parity-check codes

A secure channel coding (joint encryption-channel coding) scheme provides both data security and reliability in one combined process to achieve faster processing and/or more efficient implementation. The issue of using quasi-cyclic low-density parity-check (QC-LDPC) codes in a symmetric-key secure channel coding scheme is addressed. A set of this class of LDPC codes has recently been recommended by the NASA Goddard Space Flight Center for near-earth and deep-space communications. The proposed scheme provides an efficient error performance, an acceptable level of security and a low-complexity practicable implementation. The results indicate that the proposed scheme can efficiently employ large QC-LDPC codes to achieve a relatively smaller secret-key size to be exchanged by the sender and the receiver, and higher information rates in comparison with the previous symmetric-key McEliece-like schemes. Simulation results indicate that there is no trade-off between the error performance and the security level of the proposed scheme unlike that of the previous ones. These characteristics make the proposed scheme suitable for high-speed communications, such as satellite communication systems.     

Parallel reconfigurable decoder architectures for rotation LDPC codes

This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, twodimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architectureaware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.     

Optimal code rates for the Lorentzian channel: Shannon codes and LDPC codes

We take an information-theoretic approach to obtaining optimal code rates for error-control codes on a magnetic storage channel approximated by the Lorentzian channel. Code rate optimality is in the sense of maximizing the information-theoretic user density along a track. To arrive at such results, we compute the achievable information rates for the Lorentzian channel as a function of signal-to-noise ratio and channel density, and then use these information rate calculations to obtain optimal code rates and maximal linear user densities. We call such (hypothetical) optimal codes "Shannon codes." We then examine optimal code rates on a Lorentzian channel assuming low-density parity-check (LDPC) codes instead of Shannon codes. We employ as our tool extrinsic information transfer (EXIT) charts, which provide a simple way of determining the capacity limit (or decoding threshold) for an LDPC code. We demonstrate that the optimal rates for LDPC codes coincide with those of Shannon codes and, more important, that LDPC codes are essentially capacity-achieving codes on the Lorentzian channel. Finally, we use the above results to estimate the optimal bit-aspect ratio, where optimality is in the sense of maximizing areal density.     

Modified sum-product algorithms for decoding low-density parity-check codes

The authors deal with the sum-product algorithm (SPA) based on the hyperbolic tangent (tanh) rule when it is applied for decoding low-density parity-check (LDPC) codes. Motivated by the finding that, because of the large number of multiplications required by the algorithm, an overflow in the decoder may occur, two novel modifications of the tanh function (and its inverse) are proposed. By means of computer simulations, both methods are evaluated using random-based LDPC codes with binary phase shift keying (BPSK) signals transmitted over the additive white Gaussian noise (AWGN) channel. It is shown that the proposed modifications improve the bit error rate (BER) performance up to 1 dB with respect to the conventional SPA. These results have also shown that the error floor is removed at BER lower than 10^-6. Furthermore, two novel approximations are presented to reduce the computational complexity of the tanh function (and its inverse), based on either a piecewise linear function or a quantisation table. It is shown that the proposed approximations can slightly improve the BER performance (up to 0.13 dB) in the former case, whereas small BER performance degradation is observed (<0.25 dB) in the latter case. In both cases, however, the decoding complexity is reduced significantly     

Optimal code rates for concatenated codes on a PR4-equalizedmagnetic recording channel

At some nominal recording density, the read signal in digital magnetic recording resembles a Class IV partial response (PR4) signal and, hence, may be equalized to the PR4 shape with relatively little noise enhancement. When coding is added, for a fixed user density, the recording density must increase as a result of coding overhead, and the read signal will resemble PR4 to a lesser extent. Equalization to PR4 in this case will produce excessive noise enhancement. Thus, coding overhead (or rate) must be selected for optimum tradeoff between code strength and noise enhancement. Toward this end, we provide results for high-rate concatenated codes, assuming a Lorentzian recording channel model. In addition to examining optimal code rates, we compare parallel and serial concatenated code performance on the PR4 channel     

Maximum-girth slope-based quasi-cyclic (2, k ⩾ 5) low-density parity-check codes

A class of maximum-girth geometrically structured regular (n, 2, k ⩾ 5) (column-weight 2 and rowweight k) quasi-cyclic low-density parity-check (LDPC) codes is presented. The method is based on cylinder graphs and the slope concept. It is shown that the maximum girth achieved by these codes is 12. A lowcomplexity algorithm producing all such maximum-girth LDPC codes is given. The shortest constructed code has a length of 105. The minimum length n of a regular (2, k) LDPC code with girth g ? 12 determined by the Gallager bound has been achieved by the constructed codes. From the perspective of performance these codes outperform the column-weight 2 LDPC codes constructed by the previously reported methods. These codes can be encoded using an erasure decoding process.     

Capacity Approaching Run-Length-Limited Codes for Multilevel Recording Systems

We propose two constructions for multilevel run-length-limited (RLL) block codes for which the rates are very close to the capacity. For each code construction, we propose a variation that has the advantage of low complexity of encoding and decoding. We conducted a simulation to see the combined effect of channel coding and our proposed RLL coding over an optical recording channel.     

Multitrack Digital Data Storage: A Reduced Complexity Architecture

We describe a low-complexity noniterative detector for magnetic and optical multitrack high-density data storage. The detector is based on the M-algorithm architecture. It performs limited breadth-first detection on the equivalent one-dimensional (1-D) channel obtained by column-by-column helical unwinding of the two-dimensional (2-D) channel. The detection performance is optimized by the use of a specific 2-D minimum-phase factorization of the channel impulse response by the equalizer. An optimized path selection scheme maintains the complexity close to practical 1-D Viterbi. This scheme is based on an approximate path metric parallel sort network, taking advantage of the metrics' residual ordering from previous M-algorithm iterations. Such an architecture approaches maximum-likelihood performance on a high areal density uncoded channel for a practical number of retained paths M and bit error rate (BER) below 10^-4. The performance of the system is evaluated when the channel is encoded with multi-parity check (MPC) block inner code and an outer interleaved Reed-Solomon code. The inner code enhances the minimum error distance of the equalized channel and reduces the correct path losses of the M-algorithm path buffer. The decoding is performed noniteratively. Here, we compare the performance of the system to the soft iterative joint decoding of the read channels for data pages encoded with low-density parity check (LDPC) codes with comparable rates and block length. We provide an approximation of the 2-D channel capacity to further assess the performance of the system     

Improved parallel weighted bit-flipping decoding algorithm for LDPC codes

Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.     

Enforcing maximum-transition-run code constraints and low-density parity-check decoding

We present a novel algorithm for imposing the maximum-transition-run (MTR) code constraint in the decoding of low-density parity-check (LDPC) codes over a partial response channel. This algorithm provides a gain of about 0.2 dB. We also develop log and max-log versions of the MTR enforcer, similar to the well-known "log-MAP" (maximum a posteriori ) and "max-log-MAP" variants of the LDPC decoder, that have performance equivalent to that of the original version.     

A novel approach to generating long low-density parity-check codes using two configurations

A new low-complexity generating method is given for the construction of long low-density parity-check (LDPC) codes. The method is based on performing a combinatorial operation between two given configurations. Combinatorial structures such as lattices, affine and projective planes are considered as the constituent configurations. Using this method, we present several classes of well-structured four-cycle free LDPC codes of high rates most of which are quasi-cyclic. From among the main advantages of this approach, we may refer to its low-complexity property and the fact that from performance perspective the constructed codes compete with the pseudorandom LDPC codes.     

A Note on &#8220;Signal-to-Noise Ratio Mismatch for Low-Density Parity-Check Coded Magnetic Recording Channels&#8221; by W. Tan and J. R. Cruz

In this letter, we prove that the minimum signal-to-noise ratio (SNR) threshold of the iterative belief propagation algorithm for a low-density parity-check (LDPC) coded magnetic recording channel is obtained when the SNR mismatch factor is half the ratio of variance to mean for the Gaussian distribution at the channel output. This result was first observed by Tan and Cruz empirically     

High-rate coding system for magnetic recording

A coding system for magnetic recording channels combining a high-rate error detection code with a list Viterbi algorithm (LVA) is proposed. This coding system can provide a coding gain of up to 2-3 dB for a modified extended extended partial response class IV (EEPR4) channel. A pipelined implementation of the LVA is presented, and an accurate estimation technique for the LVA performance is developed     

Turbo-coded optical recording channels with DVD minimum mark size

Recent work on turbo codes applied to partial response (PR) optical recording channels has focused on unconstrained channels. In this paper, we consider the application of turbo codes to a (1,7) constrained, PR-equalized optical recording channel with digital versatile disc (DVD) parameters. The addition of a (1,7) run-length-limited (RLL) constraint requires the use of a soft RLL decoder to communicate with the turbo code. Although soft RLL decoders were previously developed for use with iterative decoding, application to a practical optical channel has not been addressed until now. Here, results on both correlated noise and media noise optical recording channel models are given for two PR targets, 1+D and 1+D+D²+D ³. We achieved coding gains of 4 to 6.3 dB over a baseline RLL-coded system. We also evaluated system performance at smaller mark sizes, and found that density gains of 17% and 22% are achievable for the two targets, respectively     

Application of MTR soft-decision decoding in multiple-head magnetic recording systems

Application of a simple approach for the soft-decision decoding of Maximum-Transition-Run (MTR) codes has been presented in this paper. A lowdemanded hardware realization have been proposed for soft-decision decoding in MTR basic AND, OR and XOR logic circuits. The suggested approach is explored over the two-track, two-head E²PR4 partial response magnetic recording system. The overall two-track channel detection complexity reduction of 41·9% is offered in simulation scheme, encoded by Low-Density Parity-Check (LDPC) code, serially concatenated with inner MTR. The 1·9 dB coding gain has been obtained, comparing to uncoded channel and assuming the AWGN noise presence.     

Analysis of LDPC Code in Hybrid Communication Systems

Free-space optical (FSO) communication is of supreme importance for designing next-generation networks. Over the past decades, the radio frequency (RF) spectrum has been the main topic of interest for wireless technology. The RF spectrum is becoming denser and more employed, making its availability tough for additional channels. Optical communication, exploited for messages or indications in historical times, is now becoming famous and useful in combination with error-correcting codes (ECC) to mitigate the effects of fading caused by atmospheric turbulence. A free-space communication system (FSCS) in which the hybrid technology is based on FSO and RF. FSCS is a capable solution to overcome the downsides of current schemes and enhance the overall link reliability and availability. The proposed FSCS with regular low-density parity-check (LDPC) for coding techniques is deliberated and evaluated in terms of signal-to-noise ratio (SNR) in this paper. The extrinsic information transfer (EXIT) methodology is an incredible technique employed to investigate the sum-product decoding algorithm of LDPC codes and optimize the EXIT chart by applying curve fitting. In this research work, we also analyze the behavior of the EXIT chart of regular/irregular LDPC for the FSCS. We also investigate the error performance of LDPC code for the proposed FSCS.