A clock-free decoder and continuous BLF generator for EPCglobal Gen2 UHF RFID tags

In this paper, a clock-free decoder and a continuous backscatter link frequency (CBLF) generator for EPCglobal Gen2 UHF radio frequency identification (RFID) transponders are presented. In order to reduce power consumption, the high frequency clock used in the decoder circuit is replaced by two analog integrators and two comparators. In addition, a relaxation oscillator controlled by another integrator generates a CBLF. Measurement results show that the generated CBLF meets the Gen2 protocol at all possible conditions. The total power of the decoder and CBLF generator is 0.84 μW at 1 V operating voltage. As a result, the tag with the proposed circuit can acquire longer read range and higher read rates.     

Low-power broadband quadrature signal generator based on phase-tunable dividers

This paper presents the design and experimental results of a low-power 300–960 MHz I/Q signal generator for low-IF receivers. The circuit is based on phase-tunable dividers and uses delay-locked loops, which provide phase accuracy for the quadrature signals as well as low-sensitivity of the phase error against temperature and power supply variations. Thanks to the adopted technique, the phase error can be further reduced by trimming the reference voltage of the delay-locked loops through a calibration digital word, which can be stored in a non-volatile memory during manufacturing. The I/Q generator exhibits an absolute phase error before calibration that is lower than 1.5°. The I/Q phase drift due to temperature variations from ?40 to 85 °C and power supply variations from 1.1 to 1.3 V is 0.3° and 0.2°, respectively. By dividing the overall frequency range into four 165-MHz wide sub-bands and using only four 5-bit calibration words, the I/Q phase variation with respect to frequency, temperature, and power supply is lower than 1° in the 300–960 MHz operating band. The I/Q generator is implemented in a 90-nm CMOS technology and exhibits a current consumption as low as 0.5 mA.     

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 ⁿ ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400–3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 × 1.6 mm². It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <−131dBc/Hz at 1.45 MHz offset.     

A calibrated direct conversion front-end transmitter with resonant matching techniques for mobile WiMAX/WiBro applications

A direct conversion front-end transmitter with the properties of high linearity and high single sideband rejection ratio is described in this paper. The transmitter employs two resonant matching techniques to improve its operating bandwidth. The first resonant circuit design is applied at the inter-stage of the LO input buffer in order to achieve a wideband frequency response which ranges from dc to 6 GHz. The second resonant circuit is applied at the power amplifier (PA) driver output stage to increase the matching bandwidth and meet both the Worldwide Interoperability for Microwave Access (WiMAX) and Wireless Broadband (WiBro) applications simultaneously. In addition, the sideband signal and carrier leakage of this transmitter are further minimized by a proposed calibration circuit design to achieve the error vector magnitude (EVM) specifications. The measured single sideband performance with calibration mechanism demonstrates approximately 15 dB improvement on sideband and carrier suppression. The rejected sideband and carrier signals can be up to 55.19 and 56.31 dBc, respectively. The measured dynamic gain range of the transmitter is 53 dB in 1-dB step with a maximum relative gain error lower than 0.4 dB. The transmitter delivers +0.766 dBm output power with EVM of −34.687 dB for the orthogonal frequency division multiple access (OFDMA) 64QAM-3/4 modulated signals. The measured constellation is minimized to be <1.5% with output power from −2.3 to −36.2 dBm.     

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

In this work a 2.2 GHz quadrature receiver front-end suitable for low-power applications is presented. The low-noise amplifier, the mixer and the voltage-controlled oscillator are merged into a single stage, making the circuit capable of extreme current reuse while keeping it still functional at low supply voltage. A careful linear time-variant analysis is proven to be necessary to accurately predict the conversion gain and the bandwidth of the downconverter. A prototype, implemented in a 90 nm CMOS technology, validates the theoretical analysis, showing 27 dB of downconversion gain over a 14 MHz base-band bandwidth; the noise figure is 13 dB with a flicker corner frequency of 200 kHz; the input-referred 1 dB compression point is −23.7 dBm. The circuit draws only 1.3 mA from a 1.0 V supply.     

Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer

A self-calibrated quadrature generator capable of generating local oscillator (LO) outputs for IEEE 802.11a-b is presented. The quadrature generator is embedded in a frequency synthesizer that generates reference frequencies at 2.4 and 5GHz. A new sequential calibration scheme maintains the quadrature at the 5-GHz output within a maximum phase error of 2/spl deg/, while a divide-by-two flip-flop generates the quadrature output at 2.4 GHz. The circuit is fabricated in a 0.25-/spl mu/m SiGe BiCMOS technology and occupies a silicon area of 2 mm/sup 2/; the quadrature generator consumes a current of 5 mA from a 2.5-V supply.     

A CMOS K-Band Quadrature Generator

This letter presents a K-band quadrature signal generator in a standard 0.13 mu m CMOS process. The quadrature generator operates from 18 to 21 GHz. A maximum output power of -3.7 dBm (per I or Q channel) is achieved, and the down converted signal suppression is >25 dB at the operating bandwidth. A measured sideband rejection ratio >30 dB is achieved from 19 to 21 GHz, with a peak of >40 dB at 19.5-20.5 GHz. The current consumption of the quadrature generator is 49-54 mA from a 2-2.5 V supply with an effective chip area of 0.51times 0.44 mm² . To the author's knowledge, this is the first demonstration of a K-band quadrature signal generator with high spectral purity and quadrature accuracy.     

A high-speed four-phase clock generator for low-power on-chip SerDes applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.     

A quadrature RC-oscillator with capacitive coupling

In this paper the capacitive coupling in quadrature RC-oscillators is investigated. The capacitive coupling has the advantages of being noiseless with a small area penalty and without increasing the power dissipation. The results show that a phase error below 1° and an amplitude mismatch lower than 1% are obtained with a coupling capacitance about 20% of the oscillator׳s capacitance value. Due to this kind of coupling, the phase-noise improves by 3 dB (to −115.1 dBc/Hz @ 10 MHz) and the increase of power requirement is only marginal leading to a figure-of-merit of −154.8 dBc/Hz. This is comparable to the best state-of-the-art RC-oscillators, yet the dissipated power is about four times less. We present calculations of frequency, phase error and amplitude mismatch that are validated by simulations. The theory shows that phase error is proportional to the amplitude mismatch, indicating that an automatic phase error minimization based on the amplitude mismatches is possible. The measurements on a 2.4 GHz voltage-controlled quadrature RC-oscillator with capacitive coupling fabricated in 130 nm CMOS circuit prototypes validate the theory.     

A ±3.07% frequency variation clock generator implemented using HV CMOS process

In this paper, we propose a clock generator with a feedback TPC (temperature and process compensation) bias circuit fabricated by a high-voltage (HV) CMOS process. Particularly, the feedback TPC bias is composed of an OPA, MOS transistors and resistors, where large BJT devices are no longer needed such that it is easy to be integrated on chip with small area overhead. The feedback TPC bias circuit, including a MOS transistor, four resistors, and a differential amplifier, is used to provide temperature and process compensation. The proposed circuit design is implemented using 0.25 μm 60 V BCD process. Measurement of 10 dies in the range of 0 °C to 100 °C is carried out to verify that the worst frequency drifting error is ±3.07%.     

Low power clock recovery circuit for passive HF RFID tag

A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable system clock when communication occurs from interrogator to tag with 100% ASK modulation. An envelope detector is designed to detect the incident power from interrogator and control the operating state of the proposed clock recovery circuit. Loop bandwidth of PLL circuits is minimized to reduce the frequency deviation when operating in frequency maintaining state. Furthermore, an initialization circuit for loop filter is also used to speed up locking during initial system power-on-reset. Prototype chips have been fabricated in 0.35 μm 2P4M CMOS technology. A total current consumption of 3 μA has been achieved in the frequency maintaining state. Measurement results show that, when communication occurs from interrogator to tag with 100% ASK modulation, clock recovery circuit generates a stable and consecutive system clock and has an inevitable frequency derivation of 7.5% when operating in frequency maintaining state.     

A single-bit sampling demodulator for biomedical implants

A phase-shift keying (PSK) demodulator is demonstrated for the target application of low power and high data rate inductive links. The demodulator based on the single-bit sampling demodulation scheme is capable of operating in binary, quadrature, 8-, and 16-PSK mode. The prototype chip realized in 0.18-µm CMOS process can demodulate up to 1.25 MSymbol/s at 5-MHz carrier frequency. It occupies 240×310 µm² and consumes 140 µA from 1.2 V.     

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

Radiation performance improvement of wideband microstrip antenna array using wideband AMC structure

In this paper, the radiation performance of an antenna array is improved by designing a new wideband artificial magnetic conductor (AMC). The proposed AMC surface operates at the frequency of 3 GHz with ±90^° reflection phase bandwidth of 22%. In order to identify the key design parameters of the AMC structure, a parametric study is performed. To improve the radiation performance of the antenna array, an AMC reflector is developed through utilizing an array of 2 × 8 periodic patches of AMC unit cells. By this technique, the front to back ratio of the designed antenna array is enhanced about 16.27 dB. It is concluded that tuning of the AMC dimensions for controlling the reflection coefficient at each port of antenna array during beam steering is necessary. Because of the using of the AMC surfaces as a reflector instead of conventional PEC surfaces, size reduction of the antenna array in the order of 20% is achieved. In this study, a circuit model for single element of the antenna array with considering AMC loading effect is introduced, which predicts the bandwidth behaviour of the proposed antenna. The final designed antenna array exhibits low level of cross polarization making it well‐suited for tracking radars and electronic warfare applications. The proposed antenna with the AMC reflector is fabricated and measured. The measured ?10 dB impedance bandwidth and peak gain of the proposed antenna is 20% (2.7‐3.25 GHz) and 13.4 dBi, respectively, which are compatible with the simulation results.     

Cascadable Current-Mode Biquad Filter and Quadrature Oscillator Using DO-CCCIIs and OTA

This article introduces a circuit which can function both as a quadrature oscillator and as a universal biquad filter (lowpass, highpass, bandpass). When the circuit functions as a universal biquad filter, the quality factor and pole frequency can be tuned orthogonally via the input bias currents. When it functions as a quadrature oscillator, the oscillation condition and oscillation frequency can be adjusted independently by the input bias currents. The proposed circuit can work as either a quadrature oscillator or a biquad filter without changing the circuit topology. The amplitude of the proposed oscillator can be independently controlled via the input bias currents. The proposed oscillator can be applied to provide amplitude modulated/amplitude shift keyed signals with the above-mentioned major advantages. The circuit is very simple, consisting of four dual-output second generation current controlled current conveyors (DO-CCCIIs), one operational transconductance amplifier (OTA), and two grounded capacitors. Without any external resistors and using only grounded elements, this circuit is therefore suitable for IC architecture. PSPICE simulation results are depicted here, and the given results agree well with the theoretical analysis. The power consumption is approximately 7.32 mW at ±2.5 V supply voltages.     

A novel 5.8 GHz quasi-lumped element resonator antenna

In this paper, a novel quasi-lumped element resonator antenna is presented. The proposed antenna consists of the interdigital capacitor in parallel with a straight line inductor and is fabricated on Duroid RC4003C circuit board. The entire arrangement was fed by a coaxial feed at a frequency of 5.8 GHz. The size, bandwidth and radiation patterns were studied. The proposed antenna exhibits better impedance bandwidth and significant size reduction in comparison with similar results obtained from the conventional microstrip patch antenna with similar feeding technique and resonant frequency. The size of the proposed antenna structure is 5.8 × 5.6 mm² and experimental results are shown to be in good agreement with the design simulation.     

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm². The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.     

CMOS balanced regenerative frequency dividers for wide-band quadrature LO generation

CMOS regenerative frequency dividers, based on a fully balanced Gilbert cell, are analyzed in this paper for quadrature local oscillator (LO) signal generation. Driven in opposite phase by double frequency signals, they provide quadrature waveforms while simultaneously driving large mixers LO input capacitances, thereby avoiding power hungry buffers typically required. Experimental results, carried out on 0.18 μm CMOS prototypes, show 68% bandwidth around 2 GHz center frequency, with a quadrature accuracy better than 1°, making them suitable for multi-standard wireless receivers. To keep the output amplitude constant while simultaneously minimizing the average power consumption, a digital calibration loop regulates each divider biasing current.     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency

In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm².