Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 /spl mu/m

In this letter, we report the effects of gate notching on the performance characteristics of short-channel NMOS transistor with the gate oxide thickness of 32 /spl Aring/. The significant gate-notching defect into channel region brings about the serious degradation of such transistor performances as transconductance (G/sub m/) characteristic and subthreshold swing (S/sub t/), resulting in increases of threshold voltage (V/sub TH/) and leakage current (I/sub OFF/) and the considerable reduction of drive current (I/sub ON/). We will suggest the local thickening of gate oxide as a main mechanism of its effects and show that lack of gate-to-source/drain extension (SDE) overlap may be an additional reason for the degradation of I/sub ON/ with increasing the notch depth.     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

Gate metal interdiffusion induced degradation in space-qualified GaAs PHEMTs

While gate metal sinking has been traditionally identified as the primary degradation mechanism in GaAs pseudomorphic high electron mobility transistors (PHEMTs), there is no physical demonstration of gate metal interdiffusion or understanding of the gate metal interdiffusion effect on reliability performance. This paper reviews our results on gate metal interdiffusion in 0.15-μm GaAs PHEMTs subjected to accelerated temperature lifetest. We used the techniques of focused ion beam (FIB), high-resolution energy-dispersive analysis with X-ray (EDX), and scanning transmission electron microscope (STEM). These results substantiate the observed d.c. and RF parametric evolution with respect to reverse gate leakage current (I_g), ideality factor, Schottky barrier height (Φ_BN), transconductance (G_m), I_dss, pinchoff voltage (V_po), S21, and provide insights into the effect of gate metal interdiffusion on reliability performance. The comprehensive understanding of gate metal interdiffusion induced degradation is essential for GaAs PHEMTs due to their widespread military/space applications.     

Effect of CVD-SiO/sub 2/ film on reliability of GaAs MESFET with Ti/Pt/Au gate metal

The effect of CVD-SiO/sub 2/ films on the reliability of GaAs MESFET with Ti/Pt/Au gate metal was investigated. It was found that the mean time to failure (MTTF) of MESFET with 350/spl deg/C-depositied SiO/sub 2/ was only about one-seventh of that of the ones with 440/spl deg/C-SiO/sub 2/. It was also found that, in the storage test at 300/spl deg/C for 24 hours, diffusion of Pt into GaAs was accelerated when the SiO/sub 2/ deposition temperature was lower than 380/spl deg/C. FT-IR spectra indicated that the lower deposition temperature leads to a higher concentration of the residual hydrogen in SiO/sub 2/. Thermal differential spectrometry (TDS) demonstrated that hydrogen in SiO/sub 2/ could migrate even below 300/spl deg/C. In conclusion, the residual hydrogen in SiO/sub 2/ causes the degradation phenomena.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Stress-related hydrogen degradation of 0.1-/spl mu/m InP HEMTs and GaAs PHEMTs

Hydrogen degradation of III-V field-effect transistors (FETs) is a serious reliability concern. Previous work has shown that threshold-voltage shifts induced by H/sub 2/ exposure in 1-/spl mu/m-channel InP high-electron mobility transitors (HEMTs) can be attributed to compressive stress in the gate due to the formation of TiH/sub x/ in Ti/Pt/Au gates. The compressive stress affects the device characteristics through the piezoelectric effect. This paper examined the H/sub 2/ sensitivity of 0.1-/spl mu/m strained-channel InP HEMTs and GaAs pseudomorphic HEMTs. After exposure to H/sub 2/, the threshold voltage V/sub T/ of both types of devices shifted positive. This positive shift in V/sub T/ is predicted by a model for hydrogen-induced piezoelectric effect. In situ V/sub T/ measurements reveal distinct time dependences of the V/sub T/ shifts, which are also consistent with stress-related phenomena.     

Improving gate-oxide reliability by TiN capping layer on NiSi FUSI metal gate

The impact of TiN capping layer on gate oxide reliability of NiSi fully silicided metal gate was investigated. It was found that the TiN capping layer significantly improved V/sub th/ stability and oxide reliability during negative bias temperature stress. Better life-time performance was also extrapolated for the samples with TiN capping layer.     

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.<>     

Physical identification of gate metal interdiffusion in GaAs PHEMTs

The Ti metal interdiffusion of Ti/Pt/Au gate metal stacks in 0.15-/spl mu/m GaAs PHEMTs subjected to high-temperature accelerated lifetest has been physically identified using scanning transmission electron microscopy. Further energy dispersive analysis with X-ray (EDX) analysis confirms the Ti diffusion into the AlGaAs Schottky barrier layer and the decrease of Schottky barrier height suggests the Ti-AlGaAs intermetallic formation, which is consistent with previous Rutherford backscattering spectroscopy/X-ray photoelectron spectroscopy studies. The Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus leading to a slight Gm increase, positive shift in pinchoff voltage, and S21 increase during the preliminary portion of the lifetest. Accordingly, the Ti interdiffusion effect implies that the lifetime of GaAs PHEMTs subjected to high-temperature accelerated lifetest could be dependent upon the initial thickness of the Schottky layer underneath the gate metal.     

Structural optimization of SUTBDG devices for low-power applications

In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-/spl kappa/ gate dielectrics raise the off-state current (I/sub OFF/) due to the fringing field-induced barrier lowering effect. Suppressing the I/sub OFF/ increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I/sub OFF/, devices with less abrupt S/D-channel junctions suffer a drive current (I/sub ON/) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I/sub ON/. The I/sub ON/ of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.     

Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping

The dc and RF characteristics of Si/SiGe n-MODFETs with buried p-well doping incorporated by ion implantation are reported. At a drain-to-source biasV/sub ds/ of +1 V devices with 140-nm gate length had peak transconductance g/sub m/ of 450 mS/mm, and maximum dc voltage gain A/sub v/ of 20. These devices also had "off-state" drain current I/sub off/ of 0.15 mA/mm at V/sub g/=-0.5 V. Control devices without p-well doping had A/sub v/=8.1 and I/sub off/=13 mA/mm under the same bias conditions. MODFETs with p-well doping had f/sub T/ as high as 72 GHz at V/sub ds/=+1.2 V. These devices also achieved f/sub T/ of 30 GHz at a drain current, I/sub d/, of only 9.8 mA/mm, compared to I/sub d/=30 mA/mm for previously published MODFETs with no p-well doping and similar peak f/sub T/.     

High-temperature thermal stability performance in /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As metamorphic HEMT

We report, to our knowledge, the best high-temperature characteristics and thermal stability of a novel /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As--GaAs metamorphic high-electron mobility transistor. High-temperature device characteristics, including extrinsic transconductance (g/sub m/), drain saturation current density (I/sub DSS/), on/off-state breakdown voltages (BV/sub on//BV/sub GD/), turn-on voltage (V/sub on/), and the gate-voltage swing have been extensively investigated for the gate dimensions of 0.65/spl times/200 /spl mu/m/sup 2/. The cutoff frequency (f/sub T/) and maximum oscillation frequency (f/sub max/), at 300 K, are 55.4 and 77.5 GHz at V/sub DS/=2 V, respectively. Moreover, the distinguished positive thermal threshold coefficient (/spl part/V/sub th///spl part/T) is superiorly as low as to 0.45 mV/K.     

Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition Layers

By including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition (IFT) layers, an excellent agreement in terms of both C-V and J-V characteristics is obtained between the experiment and theory for both polarities of gate voltage (V/sub G/) for the first time. The highly precise physical models for gate depletion and gate accumulation bring an oxide thickness extracted from the C-V fitting in a negative V/sub G/ close to that extracted in a positive V/sub G/. It is shown that the physical oxide thickness should be regarded as a distance between the middle points inside the IFT layers in both sides of the gate oxide. In addition, it is found that the tunnel mass is independent of the gate-oxide thickness from 14 to 28 /spl Aring/. It is also shown that the oxide-thickness dependence of the tunnel mass , is ascribable to the C-V-J-V fitting only in the case of a negative polarity of V/sub G/ while neglecting the poly-Si/SiO/sub 2/ IFT layer.     

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

New findings of interface trap passivation effect in negative bias temperature instability (NBTI) measurement for p-MOSFETs with SiON gate dielectric are reported. We show evidence to clarify the recent debate: the recovery of V/sub th/ shift in the passivation phase of the dynamic NBTI is mainly due to passivation of interface traps (N/sub it/), not due to hole de-trapping in dielectric hole traps (N/sub ot/). The conventional interface trap measurement methods, dc capacitance-voltage and charge pumping, seriously underestimate the trap density N/sub it/. This underestimation is gate bias dependent during measurement, because of the accelerated interface trap passivation under positive gate bias. Due to this new finding, many of previous reliability studies of p-MOSFETs should be re-investigated.     

Laterally scaled Si-Si/sub 0.7/Ge/sub 0.3/ n-MODFETs with f/sub max/>200 GHz and low operating bias

We report on the dc and RF characterization of laterally scaled, Si-SiGe n-MODFETs. Devices with gate length, L/sub g/, of 80 nm had f/sub T/=79 GHz and f/sub max/=212 GHz, while devices with L/sub g/=70 nm had f/sub T/ as high as 92 GHz. The MODFETs displayed enhanced f/sub T/ at reduced drain-to-source voltage, V/sub ds/, compared to Si MOSFETs with similar f/sub T/ at high V/sub ds/.     

Long-term reliability of Ti–Pt–Au metallization system for Schottky contact and first-level metallization on SiC MESFET

The stability of metal layers on semiconductors is a key issue for the device electrical performances. Therefore, the reliability of SiC/Ti/Pt/Au system was investigated using storage steady-stress testing, AES (Auger Electron Spectrometry), and SIMS (Secondary Ions Mass Spectrometry) analysis. The study was conducted on different patterns for gate and interconnection structure to underline the different reliability problems. Auger and SIMS analysis showed important modifications in the three-metal structure without reactions with the SiC substrate. The resistance degradation was assigned to interdiffusion phenomena. It was analyzed with a diffusion-controlled model. Activation energies and mean time to failure (MTF) were calculated for a failure criterion defined as a 10% increase of the resistance. Finally, the different rules of the metallization degradation in MESFET behaviours for interconnections and gate were discussed.     

Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application

In this paper, Ta/Mo interdiffusion dual metal-gate technology, which has an advantage in realizing dual gate work functions without etching of metals from the gate dielectrics, has been introduced for a FinFET. Gate-first fabrication of the FinFET was successfully implemented by optimizing the deposition and patterning of the Mo and Ta/Mo metal gates on the ultrathin fin channels. The Ta/Mo-gated n-MOS and Mo-gated p-MOS FinFET exhibit symmetrical values of Vth (0.31/$-$0.36 V), which are desirable for FinFET CMOS circuit operation with enhanced current drivability, because the threshold voltage (Vth) is reduced due to Ta diffusion in the Ta/Mo gate. It was experimentally found that the Ta/Mo interdiffusion process causes no degradation in integrity of the gate dielectric or the carrier mobility. It was also confirmed that the Ta/Mo interdiffusion process is appropriate for a scaled gate length down to 100 nm.      

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.     

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.