All-digital A/D converter TAD with high-resolution and low-power for sensor/RF digitization

For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using full-digital circuits, which deals with only two voltage levels (i.e., V _in-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation along with high scalability. The circuit architecture is completely digital, using a ring-delay-line (RDL) driven by an input voltage V _in as its power supply. Resolutions can be controlled by setting its conversion time T _cv, resulting in 16 bit (1 kS/s, 34 μW) and 6 bit (1 MS/s, 48 μW) with a prototype IC in a low-cost 0.65-μm (650-nm) digital CMOS, achieving the sensor digitizer (sensor-digitization product) of a pressure sensor ASIC. The all-digital structure has been scaled into a 0.18-μm technology, and the test IC presented a higher performance with 28 μV/LSB (160-kS/s). Finally, as an RF digitization application, the circuit is demonstrated to realize the time-domain processing of an RF signal, working as both mixer and ADC, achieving minimum/maximum detectable sensitivity of 0.7-μVrms/100-mVrms, respectively, for a 40-kHz sine wave at the LNA input terminal of a 0.18-μm digital CMOS one-chip radio-controlled clock receiver IC.     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

Integrated control circuit for adaptive sampling

A fully integrated controller for non-uniform data sampling suitable for the pre-processing of signals in a power- and size-restricted sensor front-end is presented. The sample rate is dynamically varied based on signal activity determined by the 2nd derivative of the input voltage. The derivative is realized with high-pass filters having 647 Hz cut-off frequency. A digital circuit generates the time-stamps and the trigger for an external analog-to-digital converter. Measured results of a 0.35 μm CMOS implementation show a sample rate variation of 7:1 and a system power advantage compared to conventional front-ends. The circuit dissipates 48 μW from ±1.5 V supplies and consumes an active area of 0.068 mm².     

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm². Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.     

Power management circuits for self-powered systems based on micro-scale solar energy harvesting

In this paper, two types of power management circuits for self-powered systems based on micro-scale solar energy harvesting are proposed. First, if a solar cell outputs a very low voltage, less than 0.5 V, as in miniature solar cells or monolithic integrated solar cells, such that it cannot directly power the load, a voltage booster is employed to step up the solar cell’s output voltage, and then a power management unit (PMU) delivers the boosted voltage to the load. Second, if the output voltage of a solar cell is enough to drive the load, the PMU directly supplies the load with solar energy. The proposed power management systems are designed and fabricated in a 0.18-μm complementary metal–oxide–semiconductor process, and their performances are compared and analysed through measurements.     

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V _T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm².     

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm². The BICS occupies only 41×17 μm² of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.     

A high-speed CMOS image sensor with a 11-bit column-parallel A/D converter

This article presents a high-speed, high-linearity 400 × 320 pixel CMOS image sensor with column parallel ADC. The pixel readout circuit is integrated in the 320 columns at one side of the pixel array and all columns consume 16 mW power provided from the 2.5 V power supply. A technique for accelerating conversion speed using two step single slope structure is developed. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25 μm CMOS technology. Moreover, an overall SNR of 63.8 dB can be achieved at 0.5 Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consumes 76 mW.     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

A CMOS micro power switched-capacitor DC–DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V_OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm² in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm², is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m². After starting-up, the system requires an irradiance of only 0.18 W/m² (18 μW/cm²) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels.     

A bipolar output voltage pulse transformer boost converter with charge pump assisted shunt regulator for thermoelectric energy harvesting

This system presents an energy harvesting system that generates bipolar output voltage (±1 V) based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. A shunt regulator is designed using six-transistor Schmitt-Trigger core to limit the boost converter output voltage. Another power stage, i.e. a fully integrated on-chip single-stage cross-coupled charge pump, then generates 3 V output from the unused extra output power of boost converter, which is shunted otherwise. The increased voltage headroom generated is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is designed to adaptively tracking the input voltage, which is sensed using power-saving time-domain digital technique. Based on a standard CMOS 0.13-µm technology, chip measurement verified the operations of the boost converter, shunt regulator and bipolar charge pump prototypes, respectively. Simulations confirmed the full system operations. During start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW.     

Fully integrated signal conditioning of an accelerometer for implantable pacemakers

This paper shows the development of a fully integrated G _m -C 0.5–7 Hz bandpass amplifier (gain G = 400), for a piezoelectric accelerometer to be employed in rate adaptive pacemakers. The circuit, fabricated in a standard 0.8 micron CMOS technology, operates with a power supply as low as 2 V, consumes 230 nA of current, and has only a 2.1 μV_rms input referred noise. Detailed circuit specifications, measurements, and a system performance comparative analysis are presented. The physical activity system includes a fully integrated G _m -C rectifier and 3-second time average. Fully integrated very low frequency circuits were implemented with the aid of series-parallel current division in symmetrical OTAs. OTAs as low as 33 pS (equivalent to a 30 GΩ resistor) were designed, fabricated, and tested.     

Design and fabrication of 2.4 GHz pre-biased rectifier

A 2.4 GHz rectifier operating in a region of low RF input power was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input signal. Since a rectifier needs an RF signal higher than the threshold voltage of transistors, we introduced a pre-biasing circuit to compensate for the threshold voltage. A low-voltage digital circuit, subthreshold voltage regulator, and low-power level shifter were introduced for reducing the power consumption of the pre-biasing circuit and increasing the driving voltage for the switches at the same time. The circuit simulations revealed that the pre-biasing circuit was effective in a low RF input power region. However, the output voltage was degraded in a high power region. Then, we combined the pre-biased rectifier in parallel with a non-biased rectifier. Three types of rectifiers consisting of LC matching circuits, three-stage rectifier cells, and biasing circuits were designed and fabricated using a 0.18-μm mixed signal/RF CMOS process with one poly and six metal layers. The fabricated pre-biased rectifier operated in a region of RF input power of less than ?15 dBm, while the non-biased rectifier could not operate in this region. The parallel combination of pre-biased and non-biased rectifiers effectively solved the drawback of the pre-biased rectifier in a high RF input power region.     

SCEI能量回收接口电路的设计

基于压电效应的能量回收接口电路是能量回收系统的重要组成部分,经典的接口电路有标准接口、同步电荷提取电路(SECE)、并联同步开关电感电路(Parallel-SSHI)、串联同步开关电感电路(Series-SSHI)4种。提出并设计了一种新的接口电路——同步电荷提取和翻转电路(SCEI)接口电路,完成了该接口电路在恒定激振位移情况下回收功率的理论分析和计算,并利用电子仿真软件Multisim对SCEI和4种典型接口电路的回收功率进行了仿真和比较。结果表明,SCEI接口电路性能优越,其回收功率约是SECE电路的1.5倍,且与负载无关。     

Ultra low power frequency divider for 2.45 GHz ZigBee frequency synthesizer

An ultra low power CMOS frequency divider whose modulus can be varied from 481 to 496 is presented. It has been customized to be used in 2.45 GHz Integer-N PLL frequency synthesizers utilized in ZigBee standard. Its based on swallow divider that replaces the swallow counter by a simple digital circuit in order to reduce power consumption and design complexity. Also a low power and high speed divide-by-7/8 is presented. Post layout simulation results exhibit 420 μW power consumption for 4 bit frequency divider in 2.45 GHz ISM frequency band that proves 40 % reduction compared to same previous works. All of the circuits have been designed in 0.18 μm TSMC CMOS technology with a single 1.8 V DC voltage supply.     

A comprehensive view of digital integrated electronic circuits

The present generation of digital integrated circuits is based on the batch-fabrication of interconnected transistors and diodes. These circuits successfully provide the elementary logic modules which can be directly interconnected to realize complex digital systems. The basic circuit configurations and their design must fulfill the prime requirement of signal-quantization under various operational aspects; and thus they reflect compromises between the operation speed, the noise margin, the number of fan-in and fan-out, the operating temperature range, the power dissipation, and the cost of fabricating circuit components to the required tolerance.     

A high precision temperature control system for CMOS integrated wide range resistive gas sensors

In this work we present an integrated interface for wide range resistive gas sensors able to heat the sensor resistance through a constant power heater block at 0°C–350°C operating temperatures. The proposed temperature control system is formed by a sensor heater (which fixes the sensor temperature at about 200°C), a R/f (or R/T) converter, which converts the resistive value into a period (or frequency), and can be able to reveal about 6 decades variation (from 10 KΩ up to 10 GΩ), and a digital subsystem that control the whole systems loop. This interface allows high sensibility and precision and performs good stability in temperature and power supply drift and low power characteristics so it can be used also in portable applications. Test measurements, performed on the fabricated chip, have shown an excellent agreement between theoretical expectations and simulation results. Giuseppe Ferri is an associate professor in Electronics at the Department of Electrical Engineering of L’ Aquila University, Ital. In 1993 he has been a visiting researcher at SGS-Thomson Milano, working in bipolar low-voltage op-amp design. In 1994-95 he has been visiting researcher at KU Leuven working in low-voltage CMOS design in the group of Prof. Sansen. His research activity is actually centred on the analog design of integrated circuits for portable applications (e.g., sensors and biomedicals) and circuit theory. He is co-author of a book entitled “Low Voltage, Low Power CMOS Current Conveyors”, Kluwer ed. (2003) and four text-books in Italian on Analogue Microelectronics (2005, 2006). Moreover, he is author and co-author of 74 papers on international and Italian journals and 123 talks at national and international conferences. Vincenzo Stornelli was born in Avezzano (AQ), Italy, on May 31, 1980. He received the Electronics Engineering degree (cum laude) in July 2004. In October 2004 he joined the Department of Electronic Engineering, University of L’Aquila, where he is actually involved with problems concerning project and design of integrated circuits for RF and sensor applications, CAD modelling, characterization, and design analysis of active microwave components, circuits, and subsystems. He regularly teaches courses of the European Computer patent and has regular collaborations with national corporations such as Thales Italia     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

Power management of autonomous wireless sensor node for structure health monitoring

This paper presents the design concepts of wireless sensor network system constructed with autonomous sensing nodes, which operates at extremely low power levels. At first, conventional, wired civil structure health-monitoring system is reviewed. Then, the monitoring methodology is discussed focusing quantitative measurement accuracy. Issues of node synchronized sampling, multi-layer cluster, node distance and integrated sensor node module are discussed. Also, radio transceiver protocol candidates are reviewed from the point of connection to the Internet gateway. Sensor node consists of microprocessor, sensing analog front end, and radio transceiver. Last two factors are critical for power consumption. Therefore, low duty cycle measurement is essential, in order to accomplish the ultra low power level, which is equivalent to energy harvesting source, such as piezoelectric and solar cells, sensor node power management device circuit design is demonstrated for the high-spec measurement.     

Thermoelectric Energy Harvesting Using Phase Change Materials (PCMs) in High Temperature Environments in Aircraft

Wireless, energy-autonomous structural health-monitoring systems in aircraft have the potential of reducing total maintenance costs. Thermoelectric energy harvesting, which seems the best choice for creating truly autonomous health monitoring sensors, is the principle behind converting waste heat to useful electrical energy through the use of thermoelectric generators. To enhance the temperature difference across the two sides of a thermoelectric generator, i.e. increasing heat flux and energy production, a phase change material acting as thermal mass is attached on one side of the thermoelectric generators while the other side is placed on the aircraft structure. The application area under investigation for this paper is the pylon aft fairing, located near the engine of an aircraft, with temperatures reaching on the inside up to 350 °C. Given these harsh operational conditions, the performance of a device, containing erythritol as a phase change material, is evaluated. The harvested energy reaching values up to 81.4 J can be regulated by a power management module capable of storing the excess energy and recovering it from the medium powering a sensor node and a wireless transceiver.