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混合模块无等待时间序列超前进位加法器设计 总被引:1,自引:1,他引:0
在不增加超前进位加法器模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块超前进位加法器(CLA)延迟时间公式的基础上提出了混合模块无等待时间序列超前进位加法器.给出了混合模块CLA的无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及重要性质.并在功耗、面积(资源)占用约束下,优化设计了操作位数复盖范围为10~854位的94个混合模块无等待时间序列超前进位加法器.实现了保持CLA模块速度条件下,最大限度地扩展操作位数的目的. 相似文献
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在不增加顶层进位级联超前进位加法器(TC2CLA)模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块TC2CLA的延迟时间公式的基础上提出了混合模块顶层级联超前进位加法器无等待时间序列.给出了混合模块TC2CLA无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及一系列重要性质. 相似文献
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超前进位加法器混合模块延迟公式及优化序列 总被引:4,自引:2,他引:2
为扩展操作位数提出了一种更具普遍性的长加法器结构——混合模块级联超前进位加法器。在超前进位加法器(CLA)单元电路优化和门电路标准延迟模型的基础上,由进位关键路径推导出混合模块级联CLA的模块延迟时间公式,阐明了公式中各项的意义。作为特例,自然地导出了相同模块级联CLA的模块延迟时间公式。并得出和证明了按模块层数递增级联序列是混合模块级联CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列。这一结论成为优化设计的一个设计规则。还给出了级联序列数的公式和应用实例。 相似文献
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为提高长加法器的运算速度,扩展操作位数,提出了一种加法器结构--混合模块顶层进位级联超前进位加法器(TC2CLA).该结构将层数Mi>1的CLA模块底层进位级联改为顶层超前进位单元进位级联.在CLA单元电路优化和门电路标准延迟时间tpd的基础上,由进位关键路径推导出混合模块TC2CLA的模块延迟时间公式,阐明了公式中各项的意义.作为特例,导得了相同模块TC2CLA的模块延迟时间公式.并得出和证明了按模块层数递增级联序列是混合模块TC2CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列.这一结论成为优化设计的一个设计规则.还给出了混合模块级联序列数的公式和应用实例.TC2CLA和CLA的延迟时间公式表明,在相同模块序列和不等待(组)生成、传输信号的条件下,最高位进位延迟时间及最高位和的最大延迟时间减小. 相似文献
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32位稀疏树加法器的设计改进与实现 总被引:1,自引:0,他引:1
提出了一种改进进位运算的32位稀疏树加法器。在对现有稀疏树加法器使用的进位运算算子"o"进行深入探讨的基础上,对该算子的表达式做出了适当改进,去除了原算子中进位输入须为0的前提条件,同时保留了原算子适用于稀疏树进位结构的运算特性。采用该改进算子的32位稀疏树加法器可以并行地产生进位输入分别为0和1时的一对"和"输出,并可根据需要选择输出相应的结果。在1.2V130nm典型CMOS工艺条件下,经由HSPICE仿真,改进的32位稀疏树加法器的关键路径延迟为10.8FO4。结果表明,该加法器在运算能力得到扩充的同时,在运算速度方面也具有一定优势。 相似文献
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通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。 相似文献
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文章提出了一种基于流水线设计的具有自检测功能的进位相关和加法器。该加法器包括四个8位进位相关和加法器(CDSA).一个4位超前进位单元(BLCU)和一个奇偶校验器。与普通的行波进位加法器相比,文章设计的加法器硬件实现面积仅增加3.85%,而在关键路径的延时上,该加法器要减少39.2%。 相似文献
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对数跳跃加法器的算法及结构设计 总被引:5,自引:0,他引:5
本文介绍一种新型加法器结构——对数跳跃加法器,该结构结合进位跳跃加法器和树形超前进位加法器算法,将跳跃进位分组内的进位链改成二叉树形超前进位结构,组内的路径延迟同操作数长度呈对数关系,因而结合了传统进位跳跃结构面积小、功耗低的特点和ELM树形CLA在速度方面的优势.在结构设计中应用Ling's算法设计进位结合结构,在不增加关键路径延迟的前提下,将初始进位嵌入到进位链.32位对数跳跃加法器的最大扇出为5,关键路径为8级逻辑门延迟,结构规整,易于集成.spectre电路仿真结果表明,在0.25μmCMOS工艺下,32位加法器的关键路径延迟为760ps,100MHz工作频率下功耗为5.2mW. 相似文献
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Conventional precise adders take long delay and large power consumption to obtain accurate results. Exploiting the error tolerance of some applications such as multimedia, image processing, and machine learning, a number of recent works proposed to design approximate adders that generate inaccurate results occasionally in exchange for reduction in delay and power consumption. However, most of the existing approximate adders have a large relative error. Besides, when applied to 2's complement signed addition, they sometimes generate a wrong sign bit. In this paper, we propose a novel approximate adder that exploits the generate signals for carry speculation. Furthermore, we introduce a low-overhead module to reduce the relative error and a sign correction module to fix the sign error. Compared to the conventional ripple carry adder and carry-lookahead adder, our adder with block size of 4 reduces power-delay product by 66% and 32%, respectively, for a 32-bit addition. Compared to the existing approximate adders, our adder significantly reduces the maximal relative error and ensures correct sign calculation with comparable area, delay, and power consumption. We further tested the performance of our adders with and without the sign error correction module in three real applications, mean filter, edge detection, and k-means clustering. The experimental results demonstrated the importance of reducing the relative error and ensuring the correct sign calculation for 2's complement signed additions. The outputs produced using our adder with the sign error correction module are very close to those produced using accurate adder. 相似文献
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以浮点加法器的算法设计和结构映射为例。讨论了如何进行布告同对象的ASIC系统的设计。并给出浮点加法器部分模块的VHDL描述。 相似文献
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Kernhof J. Beunder M.A. Hoefflinger B. Haas W. 《Solid-State Circuits, IEEE Journal of》1989,24(3):570-575
For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N -b addition this results in a N /2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology 相似文献
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In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP. 相似文献
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本文以异步流水乘法器的设计为例,介绍了利用FPGA进行异步电路设计的思路及方法。本设计采用两段握手协议实现异步流水乘法器,将其分解为三个核心模块:信号分支模块、异步移位模块和异步加法器模块。本文具体说明了利用硬件描述语言实现异步乘法器的方法和步骤,通过Modelsim软件进行功能仿真,并下载到Genesys板卡上进行系统测试。该教学方案有助于学生理解并掌握异步电路设计方法。 相似文献
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The advent of advanced microelectronic technologies and scale downing into nanometer dimensions has made current digital systems more susceptible to faults and increases the demand for reliable and high-performance computing. Current solutions have so far used the parity prediction scheme to increase reliability and detect fault in adder modules, but they add perceptible area overhead to the circuit. In this paper, we present two new efficient methods for fault detection and localization, in addition to the full error-correction, targeting stack-at and multi-cycle transient (MCT) faults in radix-2 signed-digit adders through a combination of time and hardware redundancy. In this study, we use the self-checking full adder that can identify a fault based on internal functionality to detect any fault in the adder modules. The detection of a fault is followed by input inversion, recomputation, and appropriate output inversion to correct the error and localize the fault. The error-correction method employs fault masking by utilizing the self-dual concept, which is based on the fact that in the presence of a fault, the designed technique results in a fault-free complement of the expected output when fed by the complement of its input operands. In addition, the existence of any fault in the input lines of the adder modules can be identified by low-cost parity checking error-detection approach, and a faulty module can be localized by comparing the faulty output from the first computation with the fault-free output from the recomputation. Based on the experimental results, the area occupied by our designs is approximately 50% that of the area used by previous designs that employ the parity prediction scheme. In addition to the area reduction, our design approaches result in a higher reliability with less power consumption and low time delay. 相似文献
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基于FPGA的算术逻辑单元设计 总被引:1,自引:0,他引:1
介绍了一种使用可编程逻辑器件FPGA和VHDL语言进行ALU设计的方法。并在加法器模块的设计中使用了超前进位的方法。使得所设计的ALU具有很好的稳定性和较高的速度。 相似文献