一种低功耗16-bit双向进位加法器设计

在地址产生单元中,循环寻址和位反序寻址需要进行大量的正向加法和逆向加法操作,加法器功耗常常在整个地址产生单元占很大比重.提出了一种基于180nm的低功耗16-bit双向进位加法器,采用传输门与互补CMOS混合结构,可进行正向和逆向加法.并在不同的电容负载情况下通过HSPICE在1.8V供电电压下对所提出加法器进行仿真,得到的功耗与功耗延时积(PDP)与传统的28T加法器相比,具有较大改进.     

超前进位加法器混合模块延迟公式及优化序列

为扩展操作位数提出了一种更具普遍性的长加法器结构——混合模块级联超前进位加法器。在超前进位加法器(CLA)单元电路优化和门电路标准延迟模型的基础上，由进位关键路径推导出混合模块级联CLA的模块延迟时间公式，阐明了公式中各项的意义。作为特例，自然地导出了相同模块级联CLA的模块延迟时间公式。并得出和证明了按模块层数递增级联序列是混合模块级联CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列。这一结论成为优化设计的一个设计规则。还给出了级联序列数的公式和应用实例。     

混合模块无等待时间序列超前进位加法器设计

在不增加超前进位加法器模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块超前进位加法器(CLA)延迟时间公式的基础上提出了混合模块无等待时间序列超前进位加法器.给出了混合模块CLA的无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及重要性质.并在功耗、面积(资源)占用约束下,优化设计了操作位数复盖范围为10～854位的94个混合模块无等待时间序列超前进位加法器.实现了保持CLA模块速度条件下,最大限度地扩展操作位数的目的.     

VirtexTM-E器件进位逻辑及其应用

本文介绍了VirtexTM-E系列器件的基本逻辑模块结构,并通过几种具体电路讨论了如何针对进位逻辑进行设计,以提高基于FPGA的数字信号处理系统的性能.     

VirtexTM-E器件进位逻辑及其应用

本文介绍了VirtexTM-E系列器件的基本逻辑模块结构,并通过几种具体电路讨论了如何针对进位逻辑进行设计,以提高基于FPGA的数字信号处理系统的性能.     

Virtex^tm—E器件进位逻辑及其应用

本文介绍了Virtex^TM-E系列器件的基本逻辑模块结构，并通过几种具体电路讨论了如何针对进位逻辑进行设计，以提高基于FPGA的数字信号处理系统的性能。     

一种采用四/五输入可配置查找表结构和优化进位链的新型FPGA

本文提出了一种FPGA可编程逻辑单元中新型的查找表结构和进位链结构。查找表被设计为同时支持四输入和五输入的结构,可根据用户需要进行配置,且不增加使用的互连资源;在新型的进位链中针对关键路径进行了优化。最后在可配置逻辑单元中插入了新设计的可配置扫描链。该可编程逻辑单元电路采用0.13μm 1P8M 1.2/2.5/3.3V Logic CMOS工艺制造。测试结果显示可正确实现四/五输入查找表功能,且进位链传播前级进位的速度在同一工艺下较传统进位链结构提高了约3倍,同时整个可编程逻辑单元的面积较之前增大了72.5%。结果还显示,本文设计的FPGA在仅使用四输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7系列FPGA;在仅使用五输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4系列FPGA。     

新颖的双输入积分器

本文介绍了二个新颖的有源RC积分器，它们的特点是有两个输入信号端、积分电容接地、电路的积分时间常数τ要大，τ0=K，而K仅取决于电阻的比值。     

CMOS可预置双边沿触发器的设计及其应用

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出一种基于CMOS传输门的双边沿触发器设计,并设置了它的直接预置控制端以使达到实用的要求。该触发器已用PSPICE程序模拟验证了具有完整的功能。使用该触发器设计时序系统的实例被演示。对模拟所得数据的计算结果表明,与采用相同功能的单边沿触发器的系统比较,由于工作频率减半可使采用双边沿触发器的系统功耗明显降低。     

Virtex~(TM)-E器件进位逻辑及其应用

本文介绍了VirtexTM -E系列器件的基本逻辑模块结构,并通过几种具体电路讨论了如何针对进位逻辑进行设计,以提高基于FPGA的数字信号处理系统的性能。     

MCML结构高速低功耗加法器设计

通过分析MCML结构的设计方法，设计了高速低功耗四位并行加法器，采用TSMC 0．25 CMOS标准工艺完成设计。该电路工作频率达到1GHz，功耗为1．5mW，用于实现高速数字系统加法器单元。     

一种高速浮点加法器的设计实现

浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。文章从浮点加法器算法和电路实现的角度给出设计方法，并且提出动态与静态结合设计进位链的方案以及前导O预测面积与速度的折衷方法。动态与静态结合设计进位链的方法有效地降低了功耗，提高了速度，改善了性能。目前已经嵌入协处理器的设计中，并且流片测试成功。     

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.     

低功耗非全摆幅互补传输管加法器

文章提出了一种新型传输管全加器,该全加器采用互补传输管逻辑（Complementary Pass-Transistor Logic）实现.与现有的CPL全加器相比：该全加器具有面积、进位速度和功耗上的优势：并且提供了进位传播信号的输出,可以更简单的构成旁路进位加法器（Carry SkipAdder）.在此全加器基础上可以实现一种新型行波进位加法器（Ripple Carry Adder）,其内部进位信号处于非全摆幅状态,具有高速低功耗的特点.HSPICE模拟表明：对4位加法器而言,其速度接近CMOS提前进位加法器（Carry Look ahead Adder）,而功耗减小了61%.适用于高性能、低功耗的VLSI电路设计.     

BSO—PROM的光学逻辑功能及其应用

本文讨论了对输入图形进行特定的编码和对器件采用不同的读写模式。仅用单个 BSO—PROM(Bi_(12)SiO_(20)单晶普克尔效应光读出器件)便实现了两个二值图形间的所有 Boolcan 逻辑,而且不需要时序地改变器件的外加电压(极性和大小),从而大大提高了 PROM 用于光逻辑运算的速度。还将这种 PROM 成功地用于光学符号代换、矩阵外积及互连网络之中。     

An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing

The design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system’s performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, power-delay product (PDP), energy-delay product (EDP), power-delay-area product (PDAP) and power-delay-area-PSNR product (PDAPP). Simulation results confirmed the superiority of the proposed Full Adder cells compared to others. For instance, the proposed 6TIFA improves PDAPP metric at least 21% and at most 76% compared to its counterparts at 0.9V power supply.     

一种新型全加器结构的设计

全加器是算术运算的基本单元，设计结构简单的全加器有利于缩小数字自理芯片的面积。根据最新的ＸＯＲ门结构设计了一种新的全加器，这种结构的一位全加器只用２０只ＭＯＳ管，对这种新的全加器，用ＰＳＰＩＣＥ进行了晶体管级模拟。结果显示，这种新的全加器能正确完成加法器的逻辑功能。     

Design and analysis of a high-performance CNFET-based Full Adder

This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C _out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.     

反转矢量透射反馈求解光电混合全加器

提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器，该加法器可以实现两输入的光学算术运算，研制成的各单元器件可用于其它各种光计算机系统中。     

Low-power,high-speed 1-bit inexact Full Adder cell designs applicable to low-energy image processing

In this paper, three novel low-power and high-speed 1-bit inexact Full Adder cell designs are presented based on current mode logic in 32 nm carbon nanotube field effect transistor technology for the first time. The circuit-level figures of merits, i.e. power, delay and power-delay product as well as application-level metric such as error distance, are considered to assess the efficiency of the proposed cells over their counterparts. The effect of voltage scaling and temperature variation on the proposed cells is studied using HSPICE tool. Moreover, using MATLAB tool, the peak signal to noise ratio of the proposed cells is evaluated in an image-processing application referred to as motion detector. Simulation results confirm the efficiency of the proposed cells.