Digital signature schemes based on factoring and discrete logarithms

Wei-Hua He (see Electron. Lett., vol.37, no.4, p.220-22, 2001) proposed a digital signature scheme based on two well-known mathematics hard problem assumptions. The security of the proposed scheme is based on the difficulties of simultaneously solving the factoring and discrete logarithm problems with almost the same sizes of arithmetic moduli. It is shown that He's scheme is not secure if attackers can solve discrete logarithm problems.     

Novel digital filter implementations using hybrid RNS-binary arithmetic

The implementation of a FIR filter using a new hybrid RNS-binary arithmetic is presented for the first time. In the new arithmetic, the data samples are represented using RNS, and hence the carry free advantage of RNS computations is retained. However, the computation performed for each modulo is implemented using conventional binary arithmetic elements which overcome the drawback of ROM-based RNS arithmetic elements that become inefficient for large moduli. The conventional binary arithmetic elements are also faster and require less area than existing memoryless RNS arithmetic elements. It is shown that the filter structures based on the new arithmetic have better performance than those based on either the conventional binary or conventional RNS arithmetic for large moduli.     

On the binary quadratic residue system with noncoprime moduli

The residue number system (RNS) appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. A development in residue arithmetic is the quadratic residue number system (QRNS), which can perform complex multiplications with only two integer multiplications instead of four. An RNS/QRNS is defined by a set of relatively prime integers, called the moduli set, where the choice of this set is one of the most important design considerations for RNS/QRNS systems. In order to maintain simple QRNS arithmetic, moduli sets with numbers of forms 2ⁿ+1 (n is even) have been considered. An efficient such set is the three-moduli set (2^2k-2+1.2^2k+1.2^2k+2+1) for odd k. However, if large dynamic ranges are desirable, QRNS systems with more than three relatively prime moduli must be considered. It is shown that if a QRNS set consists of more than four relatively prime moduli of forms 2ⁿ+1, the moduli selection process becomes inflexible and the arithmetic gets very unbalanced. The above problem can be solved if nonrelatively prime moduli are used. New multimoduli QRNS systems are presented that are based on nonrelatively prime moduli of forms 2ⁿ +1 (n even). The new systems allow flexible moduli selection process, very balanced arithmetic, and are appropriate for large dynamic ranges. For a given dynamic range, these new systems exhibit better speed performance than that of the three-moduli QRNS system     

A fault-tolerant permutation network modulo arithmetic processor

Conventional fault-tolerant modulo arithmetic processors rely on the properties of a residue number system with L redundant moduli to detect up to L/2 errors. In this paper, we propose a new scheme that combines r-out-of-s residue codes with Berger codes to concurrently detect any number of module errors without any redundant moduli. In addition, this scheme can tolerate L faults if L redundant moduli are used, and has the property of graceful degradation when the number of faulty moduli exceeds L. Finally, it is shown that the added cost for fault tolerance is much less than those were reported earlier in the literature     

4模剩余数系统FIR数字滤波器设计

基于四模余数系统的FIR滤波器将一个滤波系统分为4个彼此独立,互不影响,并行运算的子滤波通道,消除了各个子运算通道之间的进位链,加快了计算的速度,提高了滤波精度。所有模都具有2n 和2n±1的形式,电路完全基于组合逻辑电路来实现。结果表明,无论在功耗,速度,实现复杂度等方面,采用余数系统构建的FIR滤波器都优于于传统二进制FIR滤波器。     

On MultiModuli residue number systems with moduli of forms r/sup a/, r/sup b/-1, r/sup c/+1

The residue number system (RNS) is an integer system appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. One of the most important considerations when designing RNS systems is the choice of the moduli set. This is due to the fact that the system's speed, its dynamic range, as well as its hardware complexity depend on both the forms and the number of the chosen moduli. When performing high radix-r(r>2) arithmetic, moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 imply simple RNS arithmetic and efficient weighted (radix-r)-to-RNS and RNS-to-weighted (radix-r) conversions. In this paper, new multimoduli high radix-r RNS systems based on moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 are presented. These systems will be derived from some recently developed theory. Such systems including moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 are appropriate for multiple-valued logic implementations or high radix (r>2) arithmetic using binary logic. The new RNS systems are balanced, achieve fast and simple RNS computations and conversions and implement large dynamic ranges. The specific case of the binary (radix r=2) domain is also presented.     

基于新型秘密共享方法的高效RSA门限签名方案

针对传统的门限RSA签名体制中需对剩余环Z(N)中元素求逆(而环中元素未必有逆)的问题,该文首先提出一种改进的Shamir秘密共享方法。 该方法通过在整数矩阵中的一系列运算来恢复共享密钥。由于其中涉及的参数均为整数,因此避免了传统方案中由Lagrange插值公式产生的分数而引起的环Z(N)中的求逆运算。然后基于该改进的秘密共享方法给出了一个新型的门限RSA Rivest Shanair Atleman签名方案。由于该方案无须在任何代数结构(比如Z(N))中对任何元素求逆,也无须进行代数扩张,因此在实际应用中更为方便、有效。     

关于一种算术编码数据加密方案的密码分析

本文分析了一种基于算术编码的数据加密方案。如果采用原方案的加密算法,则密文表达式有误,解密算法不能得出正确的明文,且破译者能在O(n^2)内求出密钥,如果采用原方案的解密算,破译者也可在O（n^2)内求出密钥,从而彻底的攻破了这种体制。     

一种基于信任值的Ad hoc密钥管理方案

Ad hoc网络的自组织性是其最大的优点。这种自组织性和无中心性给密钥管理带来了很大的难度。论文在将网络划分为簇的基础上,利用基于椭圆曲线的分布式密钥产生算法,提出了一种基于信任值的密钥管理方案,能够选取出合适的簇首担任CA服务器,实现了完全自组织的分布式密钥管理。     

一种支持算术张成程序的密文策略属性加密方案

密文策略属性加密方案适用于云环境中密文数据的访问控制.已有的支持算术张成程序的属性加密方案多是密钥访问策略的方案,且公开参数规模较大.本文利用双对偶向量空间（Dual Pair Vector Space,DPVS）技术,提出了一个公开参数长度固定、支持算术张成程序的密文策略属性加密方案.在新方案中,将密文相关的访问控制向量与随机矩阵结合,密钥相关的属性分量与熵扩张引理中的公开参量结合,设计方法对应了熵扩张引理中给出的密文和密钥分量的形式.最后,基于素数阶双线性熵扩张引理和k-Lin困难假设,证明了该方案具有适应安全性.新方案与已有支持算术张成程序的属性加密方案相比,实现了密文访问策略、公开参数长度固定且满足适应安全性.     

An Improved Real-Quadratic-Field-Based Key Exchange Procedure

To date, the only non-group structure that has been suitably employed as the key space for Diffie-Hellman-type cryptographic key exchange is the infrastructure of a real quadratic (number or function) field. We present an implementation of a Diffie-Hellman-type protocol based on real quadratic number field arithmetic that provides a significant improvement in performance over previous versions of this scheme. This dramatic speed-up is achieved by replacing the ordinary multiplication and reduction procedures for reduced ideals by a new version of the NUCOMP algorithm due to Shanks.     

Adaptive Chosen-Ciphertext Attack on Secure Arithmetic Coding

The paper ldquosecure arithmetic codingrdquo (in IEEE Transactions on Signal Processing, vol. 55, no. 5, pp. 2263-2272, May 2007) presented a novel encryption scheme called the secure arithmetic coding (SAC) based on the interval splitting arithmetic coding (ISAC) and a series of permutations. In the current work, we study the security of the SAC under an adaptive chosen-ciphertext attack. It is shown that the key vectors used in the codeword permutation step can be recovered with complexity O(N), where N is the symbol sequence length. After getting these key vectors, we can remove the codeword permutation step, and the resulting system has already been shown to be insecure in the original paper. This implies that the SAC is not suitable for the applications where the attacker can have access to the decoder. In addition, we discuss a method to jointly enhance the security and the performance of the SAC.     

TD-SCDMA中基于实测功率的上行接纳算法

第三代移动通信系统TD-SCDMA是一种自干扰的系统,随着未来用户的增多,无线资源相对有限的情况下,有效控制干扰的要求越来越高,而呼叫接纳控制技术就是解决这一问题的关键技术之一。对传统的接纳控制算法进行研究,提出了基于实测功率的上行接纳控制算法,并计算出接入判决的门限值,以实现用户接入系统后对QoS的保证。实验表明该算法相对于传统的算法而言,判决精度更高,并且具有门限自适应的优势。     

基于椭圆曲线数字签名算法的序列号软件保护方案

结合身份的认证,提出了一种基于椭圆曲线数字签名算法的序列号保护方案,该方案包括序列号的生成和验证两部分。软件代理商利用序列号生成方案生成序列号,并利用加壳机制将序列号验证部分嵌入到软件中,用户输入的序列号经过验证后才能安装该软件。由于序列号的安全性寓于私钥而不是算法本身的安全性,只要私钥不被泄漏,破解者无法根据序列号和公钥生成新的序列号。因此,该方案具有很好的安全性和有效性。     

On entropy-constrained vector quantization using gaussian mixture models

A flexible and low-complexity entropy-constrained vector quantizer (ECVQ) scheme based on Gaussian mixture models (GMMs), lattice quantization, and arithmetic coding is presented. The source is assumed to have a probability density function of a GMM. An input vector is first classified to one of the mixture components, and the Karhunen-Lo`eve transform of the selected mixture component is applied to the vector, followed by quantization using a lattice structured codebook. Finally, the scalar elements of the quantized vector are entropy coded sequentially using a specially designed arithmetic coder. The computational complexity of the proposed scheme is low, and independent of the coding rate in both the encoder and the decoder. Therefore, the proposed scheme serves as a lower complexity alternative to the GMM based ECVQ proposed by Gardner, Subramaniam and Rao [1]. The performance of the proposed scheme is analyzed under a high-rate assumption, and quantified for a given GMM. The practical performance of the scheme was evaluated through simulations on both synthetic and speech line spectral frequency (LSF) vectors. For LSF quantization, the proposed scheme has a comparable performance to [1] at rates relevant for speech coding (20-28 bits per vector) with lower computational complexity.     

基于FPGA乘法器架构的RNS与有符号二进制量转换

RNS(余数数制系统)是一种整数运算系统,在粒度精确性,能源损耗和响应速度上有很大的优势.从RNS到二进制数的输入输出转换是基于余数算法的专用架构实现的关键.本文提出了一个基于N类模的RNS与有符号二进制量的通用转换算法在FPGAs的乘法器上的实现过程.该算法能更有效地进行有符号数与RNS的转换.基于该算法类型乘法器在同类型乘法器中显示出了速度优势.文章中该架构被映射到Altera的10K系列的FPGA上.     

基于MTK平台的用户自定义定时来电防火墙的实现

首次提出并完成了一种基于MTK平台的、切实可行的用户自定义定时来电防火墙解决方案,该方案的优势在于手机用户可以分别设置来电接听和拒接清单,并根据自定义的规则对来电进行分时段处理。首先给出了该方案的功能描述以及软件总体设计结构图;随后深入讨论了用户自定义规则中的时段冲突判决算法以及分时来电处理判决算法;并进一步站在MTK平台的应用层到协议层的角度上,剖析了在该方案中手机来电拒接的流程;最后简要讨论了在该方案中针对MTK平台NVRAM的读写操作。     

Secure coverage-preserving node scheduling scheme using energy prediction for wireless sensor networks

With the fast development of the micro-electro-mechanical systems(MEMS),wireless sensor networks(WSNs)have been extensively studied.Most of the studies focus on saving energy consumption because of restricted energy supply in WSNs.Cluster-based node scheduling scheme is commonly considered as one of the most energy-efficient approaches.However,it is not always so efficient especially when there exist hot spot and network attacks in WSNs.In this article,a secure coverage-preserved node scheduling scheme for WSNs based on energy prediction is proposed in an uneven deployment environment.The scheme is comprised of an uneven clustering algorithm based on arithmetic progression,a cover set partition algorithm based on trust and a node scheduling algorithm based on energy prediction.Simulation results show that network lifetime of the scheme is 350 rounds longer than that of other scheduling algorithms.Furthermore,the scheme can keep a high network coverage ratio during the network lifetime and achieve the designed objective which makes energy dissipation of most nodes in WSNs balanced.     

An Efficient Scalable RNS Architecture for Large Dynamic Ranges

This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved . Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.