电源监视和控制器件

ADI公司提供业界极佳的电源监视和控制IC；ADM106x系列：带公差控制的多电源Super Sequencer^TM系列IC；ADM120x系列：为多电源系统提供±100mV精度的可级联的电源跟踪控制器；应用监视定时器监控电路检测微处理器和DSP代码执行错误；监视电源电压的低成本方法；利用ADI公司的Simple Sequencer^TM IC发挥您的电源最大功效；ADI公司提供从高速到低功耗的各种比较器满足您的设计需求；采用ADI公司的低电压和高电压热插拔控制器避免背板瞬态尖峰电流造成的严重经济损失；利用ADI公司最新系列2．7V RS-232收发器改进便携式设备的电源供电和数据速率；     

采用5V单电源供电的通信收发器LMS202E/LMS485及其应用

介绍了采用单5V电源工作的RS-232通信双收发器LMS202E和高速双向数据通信差分总线收发器LMS485的主要特性 ,给出了它们的典型应用电路。     

从RS232口获取+5 V电源

由于RS232通信接口协议简单,工业控制系统已广泛应用RS232口对各种设备进行信号采集和控制。为了降低成本,缩小体积,这些输入输出设备可直接从RS232口获取控制电路所需的＋5V电源。文中介绍了从RS232口得到＋5V电源的几种变换电路。     

MAXIM公司专递

本期的MAXIM公司专递将介绍该公司的异步通讯接口电路。这些电路都是用于RS-232和EIA/TIA-562协议的实现,内部都具有用于电压升高和极性转换的电荷泵,—般只需单一的+5V电源(RS-232协议)或+3.3V(EIA/TIA-232协议)供电即可。     

Artesyn公司1／4砖DC／DC变换器

Artesyn Technologies公司为其Typhoon系列板上安装电源系列增添200W1／4砖DC／DC系列。它们采用与所有其它Typhoon砖式电源相同的变换拓扑架构，这种架构既能对精密同步整流的原边和副边电路实现先进的处理器控制，又能避免光电耦合器的使用。该变换器称为“ultra”系列，可提供2．5V、3．3V和15．0V的单路隔离输出，     

康佳、松下彩电“双开关电源”的原理与维修技巧

康佳T2512A和松下TC-25V30R彩电的开关电源电路基本相同，只是元件的编号不同。采用相同的开关电源电路的还有康佳T2510A、T2510B、T2510N、T2512A、T2512B、T2512N、T2516，T2517、T2910A、T2910N、T2916A、T2916N和松下TC-29V30R、TC-26V2、TC-26V2H、TC-29VIR、TC-29V2H、TC-33V2H等系列彩电。该类彩电电源电路采用分立元件组成，主、副电源电路均为开关电源，故称其为“双开关电源”。     

一种用于高速锁相环的新型CMOS电荷泵电路

提出了一种适用于高速锁相环电路的新型CMOS电荷泵电路。该电路利用正反馈电路提高电荷泵的转换速度，利用高摆幅镜像电流电路提高输出电压的摆动幅度，消除了电压跳变现象。电路设计和H-SPICE仿真基于BL 1．2μm工艺BSIM3、LEVEL=47的CMOS库，电源电压为2V，功耗为0．1mW。仿真结果表明，该电路可以很好地应用于高速锁相环电路。     

PA-Cap聚合物电容器在模拟CPU电源中的应用

在计算机CPU的电源电路中,采用电解电容器作为电源的去耦电容。研究了CPU的负载高速变化时,三种类型电容器提供瞬时电流以稳定电源电压的情况。结果显示:PA-Cap聚合物片式叠层铝电解电容器(56μF)的Res为23mΩ,△V为–90mV,而220μF钽电容Res为73mΩ,△V为–172mV,1000μF液体铝电解电容Res为56mΩ,△V为–232mV。因此,PA-Cap聚合物电容器用在开关电源和数字电路中应用前景广阔。     

RS-232收发器接口芯片SP3223E/3243E 的原理及应用

SP3223E/3243E是SIPEX公司生产的RS -232收发器接口芯片。该器件内部含有一个高效电荷泵 ,可在单 3.0V～ 5.5V电源下产生±5.5V的RS -232电平 ,并支持EIA/TIA -232和ITU -TV.28/V.24通信协议 ,因而可用于笔记本电脑等便携式设备。文章分析了SP3223E/3243E的结构原理和主要特点 ,给出了它的典型应用电路     

康佳、松下彩电"双开关电源"的原理与维修技巧

康佳T2512A和松下TC-25V30R彩电的开关电源电路基本相同,只是元件的编号不同。采用相同的开关电源电路的还有康佳T2510A、T2510B、T2510N、T2512A、T2512B、T2512N、T2516、T2517、T2910A、T2910N、T2916A、T2916N和松下TC-29V30R、TC-26V2、TC-26V2H、TC-29V1R、TC-29V2H、TC-33V2H等系列彩电。该类彩电电源电路采用分立元件组成,主、副电源电路均为开关电源,故称其为"双开关电源"。     

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25-mum SOS-CMOS technology, occupies 35times25 mum² and exhibit a operating frequency of 5.6 GHz while consuming 79 muW at a supply voltage of 0.8 V. Process and temperature tolerant operation can be achieved by utilizing a novel compensation circuitry to calibrate the speed of the ring oscillator-based divider. The simple compensation circuitry contains low-speed digital logic and dissipates minimal additional power since it is powered on only during the one-time factory calibration sequence     

A wireless implantable multichannel digital neural recording systemfor a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of ±500 μV neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 μs/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4×4 mm² of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4×6 mm² of area     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

A Modular Fuel Cell, Modular DC–DC Converter Concept for High Performance and Enhanced Reliability

Fuel cell stacks produce a dc output with a 2:1 variation in output voltage from no-load to full-load. The output voltage of each fuel cell is about 0.4 V at full-load, and several of them are connected in series to construct a stack. An example 100 V fuel cell stack consists of 250 cells in series and to produce 300 V at full-load requires 750 cells stacked in series. Since fuel cells actively convert the supplied fuel to electricity, each cell requires proper distribution of fuel, humidification, coupled with water/thermal management needs. With this added complexity, stacking more cells in series decreases the reliability of the system. For example, in the presence of bad or malperforming cell/cells in a stack, uneven heating coupled with variations in cell voltages may occur. Continuous operation under these conditions may not be possible or the overall stack output power is severely limited. In this paper, a modular fuel cell powered by a modular dc–dc converter is proposed. The proposed concept electrically divides the fuel cell stack into various sections, each powered by a dc–dc converter. The proposed modular fuel cell powered by modular dc–dc converter eliminates many of these disadvantages, resulting in a fault tolerant system. A design example is presented for a 150-W, three-section fuel cell stack and dc–dc converter topology. Experimental results obtained on a 150-W, three-section proton exchange membrane (PEM) fuel cell stack powered by a modular dc–dc converter are discussed.      

A new design of power supplies for pocket computer systems

A new design of power supply based on the idea of switched capacitors, as applied to pocket computer systems, is presented. This new type of power supply is inductorless and, consequently, suitable for hybridization and even monolithic integration. The new design is also based on distinguishing characteristics of pocket digital computer systems, in which a switched-capacitor converter can work well, since minimal regulation is required. The new device may enable the pocket computer system to be powered by only one battery, resulting in a simple topology. Two switched-capacitor converters, +12 V/-12 V, +5 V and +5 V/+12 V, -12 V, are shown, respectively, as an example for demonstrating the basic principle and its performance. PSPICE simulation and laboratory models show good results for this new type of power supply     

用于通信ASIC的高速BiCMOS逻辑电路

提出了几种通信用BiCMOS逻辑门电路的实现方案。这些逻辑门均可在低电源电压(2.0~3.0 V)下,采用BiCMOS工艺和深亚微米技术精心设计及制作,并经过比较对其作出评价。分析和实验结果表明,所设计的电路不但具有确定的逻辑功能,而且具备高速、低耗、低电源电压和全摆幅的特性,因而完全适用于高速数字通信系统中。     

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm(2) of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested.     

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.     

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.