Model partitioning and the performance of distributed timewarp simulation of logic circuits

Simulation of complex digital electronic systems requires powerful machines and algorithms. Distributed simulation could improve both the execution time and the availability of a large distributed memory for complex models. Model partitioning onto the available processors has a major impact on simulation efficiency. We report on how various partitioning algorithms affect timewarp-based distributed simulation of combinational and synchronous sequential logic circuits, and try to determine the relationship between circuit parameters (the number of gates, topological levels and the degree of activity in the circuit) and the structure of the partition having the fastest simulation on a heterogeneous network of Sun workstations.     

下三角矩阵神经网络逻辑电路的设计

由于人工神经网络的卓越优点，为制造超高速，高可靠和可编程的数字集成电路提供了新途径，具有下三角形连接矩阵的Ｈｏｐｆｉｅｌｄ模型在同一输入下仅有唯一的平衡点。本文将讨论基于这种网络模型的组合逻辑电路的逻辑设计方法，以最小化神经元个数为目标的启发式优化算法及权电阻网络参数的计算方法。     

数字电路门级并行逻辑模拟

对基于事件驱动的电路门级并行逻辑模拟算法和相应的电路划分算法进行了研究。在保守协议的基础上,模拟算法采用流水线技术避免了死锁;采用事件打包,消息队列和非阻塞通讯技术减少了消息传递开销。在聚集分解的基础上,电路划分算法对组合或时序电路都可进行非循环划分,保证流水线模拟不会出现死锁。在曙光集群上采用MPI实现了模拟算法,对ISCAS部分电路进行实验,获得了很好的加速比。最后提出采用预模拟方法的电路划分改进方案。     

组合逻辑电路的软错误率自动分析平台

为在设计阶段快速评估集成电路的软错误率,以指导高可靠集成电路的设计,提出一种适用于组合逻辑电路和时序逻辑电路组合逻辑部分的快速软错误率自动分析平台HSECT-ANLY.采用精确的屏蔽概率计算模型来分析软错误脉冲在电路中的传播;用向量传播和状态概率传播的方法来克服重汇聚路径的影响,以提高分析速度;使用LL(k)语法分析技术自动解析Verilog网表,使分析过程自动化,且使得本平台可分析时序电路的组合逻辑部分.开发工作针对综合后Verilog网表和通用的标准单元库完成,使得HSECT-ANLY的实用性更强.对ISCAS'85和ISCAS'89 Benchmark电路进行分析实验的结果表明:文中方法取得了与同类文献相似的结果,且速度更快,适用电路类型更多,可自动分析电路的软错误率并指导高可靠集成电路的设计.     

A new automated design and optimization method of CMOS logic circuits based on Modified Imperialistic Competitive Algorithm

This paper proposes a novel evolutionary approach based on modified Imperialist Competitive Algorithm for combinational logic circuits designing and optimization. The Imperialist Competitive Algorithm operates on real values and is not applicable to logic circuits optimization problems. So a modified version of ICA is proposed to overcome this shortcoming. Modification of the algorithm depends on random cell replacement between Imperialist and its colonies as assimilation policy. Also a multi-objective evaluation mechanism in the form of a weighted cost function is introduced to obtain optimized circuits in case of circuit area and propagation delay. To evaluate the effectiveness of this method some general benchmark circuits are used in which the circuits with fewer logic cells (minimized space) and lower propagation delay are obtained. The simulation results of our proposed method are compared with some conventional and heuristic methods. Simulation results show that our proposed method significantly improves the performance factor which represents both circuit area and propagation delay.     

Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits

Experimental results show that parallel programs can be evolved more easily than sequential programs in genetic parallel programming (GPP). GPP is a novel genetic programming paradigm which evolves parallel program solutions. With the rapid development of lookup-table-based (LUT-based) field programmable gate arrays (FPGAs), traditional circuit design and optimization techniques cannot fully exploit the LUTs in LUT-based FPGAs. Based on the GPP paradigm, we have developed a combinational logic circuit learning system, called GPP logic circuit synthesizer (GPPLCS), in which a multilogic-unit processor is used to evaluate LUT circuits. To show the effectiveness of the GPPLCS, we have performed a series of experiments to evolve combinational logic circuits with two- and four-input LUTs. In this paper, we present eleven multi-output Boolean problems and their evolved circuits. The results show that the GPPLCS can evolve more compact four-input LUT circuits than the well-known LUT-based FPGA synthesis algorithms.     

基于多目标自适应遗传算法的逻辑电路门级进化方法

提出一种改进的遗传算法，通过网表级编码、多目标评估和遗传参数自适应等措施，可依据多个设计目标，以较少的运算量自动生成和优化逻辑电路．在数字乘法器、偶校验器等进化设计实验中，通过比手工设计和同类方法更优的新奇设计结果展示了该方法的有效性和先进性．     

Dynamically changing the logical behavior of the microcomputerinterface

Industrial programmable controllers and hardware simulators currently use the software method of direct logic simulation. In this method, programs contain the logical functions of several Boolean variables that are encoded directly. Each combinational circuit expressed by a group of Boolean equations requires an independent program. An alternative solution for the software implementation of the Boolean equations, named the product terms method, is presented. This method features the use of a single program to implement any multiple-output combinational circuit. To make the distinction between different circuits, a block of data defines each circuit. The product method is extended to synchronous sequential circuits, for which two tables are used. One table determines the next state of the combinational circuit, and the second table determines the outputs. An expert system has been developed to generate the table used in the product terms by interpreting the symbolic Boolean equations supplied by the user. The implementation and testing of the method are described     

Modelling and simulation of combinational digital circuits using Petri nets

The P-model approach of modeling a combinational digital network using Petri nets is introduced. In this model a given logic circuit its represented by a graph With only two types of nodes, places and transitions. A logic 1 value in any line of the circuit corresponds to the presence of a so-called token, and a logic 0 corresponds to the absence of tokens, in the corresponding place of the P-model. The operation of the circuit is reflected in the execution of the P-model resulting from the firing of transitions. Several minimizing transformations in the P-model domain are discussed, which reduces the number of places and transitions by an order of magnitude. Based on this P-model representation of a logic circuit, a logic simulation algorithm is outlined. The method is faster and also simpler to implement than conventional simulation techniques.     

基于布尔过程的组合电路波形模拟

工作频率高和定时严格是现代集成电路的特点,它们要求数字系统模拟器不但可以模拟电路的逻辑行为,而且可以精确地模拟电路的定时特性。文中提出了一个基于布尔过程的波形模拟途径,并介绍了它的理论基础、主要算法思想、所采用的技术、SPICE验证以及实验结果。     

A generalized fault simulator for combinational logic circuits

A generalized approach to the design of fault simulator using a library of simulation primitives is presented in this paper. A comprehensive set of simulation primitives has been developed using C programming language on the IBM PC. This library of simulation primitives has been used in realizing a fault simulator for automatic test pattern generation in combinational logic circuits. The fault simulator employs a combination of random pattern generation, concurrent fault simulation and the FAN algorithm for generating the complete set of test vectors to cover all the faults in the fault dictionary of the circuit under test. The library of simulation primitives is general enough to facilitate the development of fault simulators using any other test algorithms such as DALG or PODEM.     

基于概率签名的硬件木马检测技术

针对集成电路芯片被植入硬件木马后带来的安全问题,提出一种基于概率签名的硬件木马检测技术。通过逻辑功能检测,采用随机算法构建芯片电路（布尔函数）的概率签名,作为唯一的识别符模板,当被测电路的签名与模板不匹配时发出告警。设计全加器和AES加密2款电路,植入常见硬件木马并进行攻击实验,对这2种电路的原始电路以及植入硬件木马后电路的概率签名是否发生改变进行理论分析与研究。采用统计学参数估计法在FPGA平台进行实验,结果表明,该概率签名技术能检测出一般规模组合逻辑电路中植入的硬件木马,置信度达到95％。     

Modeling Combinational Circuits Using Linear Word-level Structures

In many applications of circuit design and synthesis, it is natural and in some instances essential to manipulate logic functions and model circuits using word-level representations and arithmetic operations in contrast to bit-level representations and logic operations. This paper reviews linear word-level structures and formulates their properties for combinational circuit modeling. The paper addresses the following problem: given a library of gates with their corresponding word-level representations such as linear arithmetic expressions or respective graph structures, find a word-level model of an arbitrary combinational circuit/netlist using that library of gates and minimizing memory allocation and time delay requirements. We present a comprehensive study on linearization assuming various circuit processing strategies. In particular, we develop a new approach to manipulate linear word-level representations by means of cascades. The practical applicability of linear structures and developed algorithms is strengthen by considering the problem of timing analysis. All this is supported by the experimental study on benchmark circuits.     

A method for predictive performance of distributed programs

We present a method for performance evaluation and prediction of programs running on a heterogeneous distributed system. The method is hybrid, in that it is based on the construction of a formal Petri net model of the program, supplemented with quantitative information obtained with program monitoring and architecture benchmarking techniques. The desired performance indices are computed via simulation, through net execution. The proposed method can be automated to a large extent. We show the application of the method to the evaluation of tasks or data allocation strategies on a network of workstations. The results of the experiments with two case studies are discussed.     

An efficient method of determining functional equivalence classes of a network with reconvergent fan-out

This paper is a study of the effects of the faults on tho functional operation of a combinational logic circuit. The conditions whereby two different faults can produce tho sancio functional output arc investigated. In this approach two fault graphs of the circuits arc drawn. By manipulating these fault graphs the faults which are functionally equivalent can be obtained. An algorithm for determining the functionally equivalent classes of faults in a combinational circuit is presented. The unique feature of the algorithm is that it produces tho true functional equivalence (not structural equivalence) even for the circuit with reconvergent fan-out with unequal parity.     

Intelligent design and planning of manual assembly workstations: A neuro-fuzzy approach

The design of manual assembly workstations, as with most forms of designs, is highly iterative and interactive. The designer has to consider countless constraints and solutions for contradictory goals. In order to assist the designer in design process, it is required to develop a new intelligent methodology and system. This paper develops a neuro-fuzzy hybrid approach to intelligent design and planning of manual assembly workstations. Problems, related to workstation layout design, planning, and evaluation, are discussed in detail. A fuzzy neural network is used to predict the ranges of anatomical joint motions and to design or adjust workstations and tasks. The neuro-fuzzy computing scheme is integrated with operator's posture analysis and evaluation. For training and test purposes, experiment is carried out to simulate assembly tasks on a multi-adjustable assembly workstation equipped with a flexible PEAK motion measurement and analysis system. The trained neural network is capable of memorizing and predicting the joint angles associated with a range of workstation configurations. Thus, it can also be used for the design/layout and on-line adjustment of manual assembly workstations. Thus, the developed system provides a unified, computational intelligent framework for the design, planning and simulation of manual assembly workstations.     

抗辐射集成电路单粒子激光试验与仿真分析

使用脉冲激光模拟单粒子效应技术,对抗辐射集成电路进行激光实验,找到抗辐射集成电路版图上的引起单粒子翻转的敏感位置。通过抗辐射集成电路版图与逻辑图对照和对抗辐射集成电路逻辑功能分析,在抗辐射集成电路逻辑功能框图中找到引起单粒子翻转的逻辑功能块,分析该逻辑功能块中信号的属性、信号传输的方向、信号强弱、信号对单粒子敏感程度,最终找到在脉冲激光模拟单粒子试验中出现逻辑功能错误的MOS器件。使用仿真软件模拟辐照试验中的单粒子干扰,对发生逻辑功能错误的MOS器件进行仿真,通过调整MOS器件的宽长比属性和仿真激励模型,找到逻辑功能错误的MOS器件的属性与发生单粒子翻转现象之间的联系,最终找到解决该集成电路单粒子翻转问题的方案并验证成功。     

基于布尔可满足性的电路设计错误诊断算法

提出了一种组合电路设计错误诊断算法,该算法结合传统基于模拟的方法和可满足性问题求解技术,在不依赖于故障模型的条件下实现对电路逻辑错误的诊断定位．提出了基于布尔可满足性的增量式电路诊断方法,通过对可满足解依据电路结构信息筛选分级,提高了多错误诊断定位的分辨率和准确性;并提出多项启发式方法,避免了大量不必要的操作,使算法在时间和内存上保持有效性．实验结果表明,利用形式验证的技术来导向模拟的过程,抓住了高复杂度的多错误定位问题的特征,提高了电路错误诊断的效率．     

基于仿真数据的神经网络故障诊断方法

针对某些模拟电路的历史故障信息,专家知识及其诊断经验难以获取的状况,提出了一种基于仿真数据的神经网络故障诊断方法.通过使用PSpice电路仿真软件模拟实际电路,生成训练样本训练神经网络,从而建立了电路的输出响应与电路中元件实际值之间的映射.以电路的输出响应和技术指标为判断依据,诊断电路的当前状态,定位故障元件及其偏差.最后以带通滤波器电路为例,对整个过程进行了仿真试验,验证了方法的可行性.     

Development of a user friendly gate-level logic simulator

A design of a digital logic simulator is developed and presented. BASIC on an IBM Personal Computer using interactive graphics tools is employed to make the simulator easy to use. The simulator can handle gate level logic circuits, and can be used for both logic verification and fault testing.

Efficient and correct simulation in a user-friendly environment was the main design objective. Concepts of interactive computer graphics are extensively applied to enable the drawing of the circuit. Menu structures have been used to simplify the interaction of user and computer. The foundation has been laid for a simulator that uses pattern recognition for circuit data acquisition.

The simulator permits the verification of the logic of a circuit without fault. The design also includes provision for inserting delays and simulating to detect hazards. Test sequences to detect the presence of faults in the circuit can be generated using deductive simulation. The design provides a reliable basis for further research into logic simulation.