Stacked Gate FinFET with Gate Extension for Improved Gate Control

Russian Microelectronics - Referring to the experimental data available, a modified pile gate bulk FinFET device with trapezoidal cross-section is analyzed through this paper. Two special features...     

考虑NBTI效应的逻辑门退化延迟模型

基于45 nm PTM模型,采用Hspice对基本逻辑门进行了仿真,并使用Matlab对仿真数据进行了三维延迟曲面拟合。在这些仿真基础上,建立了关于输入信号翻转时间t_i、输出负载电容CL、阈值电压变化量ΔV_th的传播延迟t_p和输出翻转时间t_o的计算模型。采用时延模型对基准测试电路ISCAS85-C17进行了计算,并将计算结果与Hspice仿真数据进行了对比。结果表明,在仿真范围(t_i=0~100 ps,CL=0~2 fF,ΔVth =0~50 mV)内,该时延模型计算值与仿真数据的相对误差在±10%以内。该模型及其计算方法可适用于大规模数字IC的可靠性设计。     

考虑门逻辑功能的最长路径搜索算法

在静态时序分析中,寻找最长时延路径以及最坏情况下时延是最重要的任务。考虑门的逻辑功能,提出了一种精度更高的最长路径搜索算法。由于门的时延大小不仅取决于输入信号的过渡(transition)时问和负载电容大小,还取决于输出信号的状态(上升或下降)以及其它管脚状态(高电平或低电平),因此,该算法极大地提高了静态时序分析的精度。文章还给出了区段搜索算法,可以找出时延在给定范围内的所有路径。这两个搜索算法对每务边至多遍历一次,时问复杂度依然为线性。     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

Power MOSFET栅电荷分析及结构改进

本文从驱动电路设计者的角度对MOS器件的输入电容和密勒电容进行了详细分析,并从器件基本原理上,对决定栅电荷的寄生元件在不同的栅电压下对栅电荷的作用进行了系统的阐述.最后总结了当前国际上为降低栅电荷提出的最新MOS器件结构.     

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property

This paper presents a statistical leakage estimation method for FinFET devices considering the unique width quantization property. Monte Carlo simulations show that the conventional approach underestimates the average leakage current of FinFET devices by as much as 43% while the proposed approach gives a precise estimation with an error less than 5%. Design example on subthreshold circuits shows the effectiveness of the proposed method.     

车库门逻辑控制系统的研究

介绍了车库门逻辑控制系统的技术要求，给出了逻辑控制系统的功能框图和以87LPC767单片机为核心的开关门控制及负载检测反馈放大电路。同时介绍了逻辑控制器软件各功能模块的作用及指令控制系统。对软件调试及实际运行试验中出现的问题进行了讨论。     

An Advanced Effective Capacitance Model for Calculating Gate Delay Considering Input Waveform Effect

In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance Ceff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.     

天然气门站站控系统的发展与应用

文章讲述天然气门站站控系统的发展及应用.通过天然气门站站控系统的设计与开发,介绍了门站站控系统的功能、组成、性能及特点.实践证明,天然气门站站控系统操作简便、数据采集准确、运行可靠,具有较大的应用价值.     

Bi-mode逆导门极换流晶闸管结构与特性研究

Bi-mode逆导门极换流晶闸管(BGCT)是为了改善传统逆导门极换流晶闸管(RC-GCT)电流均匀性和提高硅片有效面积利用率而提出的一种新结构。通过分析BGCT器件的版图布局结构,采用Sentaurus TCAD软件模拟并分析了BGCT、传统结构RC-GCT和IGCT传统功率器件的通态特性、正向阻断特性和关断特性,着重比较了RC-GCT与BGCT在400K温度下不同工作模式下特性差异。分析研究结果表明,BGCT器件能够改善RC-GCT器件的通态特性,提高硅片面积的利用率。     

静电屏蔽晶体管GAT的结构研究

本文介绍了静电屏蔽晶体管（ＧＡＴ）的结构与器件性能，该器件具有高耐压，高速和低饱和压降等优良特性。本文对该器件的结构作了较为详细的分析研究。     

Ka波段GaN HEMT栅结构仿真研究

为了研究适合Ka波段GaN HEMT的栅结构尺寸,借助二维器件仿真软件Silvaco Atlas,在完善仿真模型的基础上研究了T型栅各部分对GaN HEMT特性的影响,包括栅长与短沟道效应的关系、栅与沟道距离对短沟道效应和饱和漏电流的影响,以及栅金属厚度对最大震荡频率,栅场板对截止频率、最大震荡频率和内部电场的影响。根据典型器件结构和材料参数的仿真表明,为了提高频率并减轻短沟道效应,栅长应取0.15~0.25um;减小栅与沟道的距离可略微改善短沟道效应,但会明显降低器件的饱和漏电流,综合考虑栅调制能力、饱和漏电流、短沟道效应三个方面,栅与沟道距离应取10~20nm;为了提高最大振荡频率,栅金属厚度应大于0.4um;缩小栅场板长度可有效提高器件的频率,兼顾Ka波段应用和提高击穿电压,栅场板长度应在0.3~0.4um左右。仿真得出的器件性能随结构参数的变化趋势以及尺寸数据对于Ka波段GaN HEMT的研究具有参考意义。     

噪声门的应用及调控技巧

分析了噪声门在扩声和录音声场中噪声抑制的工作原理及其广泛应用,并从实践的角度提出了噪声门的调控技巧．并指出了噪声门的局限性。     

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis (SSTA) with process variation and prerouting interconnect delay uncertainty for field-programmable gate arrays (FPGAs). Evaluated by SSTA using the placed and routed circuits, the stochastic clustering, placement, and routing reduce the mean delay by 5.0%, 4.0%, and 1.4%, respectively, and reduce the standard deviation of delay by 6.4%, 6.1%, and 1.4%, respectively for MCNC designs. The majority of improvements come from modeling interconnect delay uncertainty for clustering and from considering process variation for placement, while routing has less improvement on delay. In addition, we study the interaction between each individual design stage. When applying all stochastic algorithms concurrently, the mean delay and standard deviation are reduced by 6.2% and 7.5%, respectively. On the other hand, stochastic clustering with deterministic placement and routing is a good flow with little change to the entire flow, but the mean delay is reduced by 5.0%, the standard deviation is reduced by 6.4%, and the runtime is slightly reduced compared to the deterministic flow. Finally, while its improvement over timing is small, stochastic routing is able to reduce the total wire length by 4.5% and to reduce the overall runtime by 4.2% compared to deterministic routing.     

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.     

声子之间相互作用对表面磁极化子有效质量的影响

本文研究极性晶体中电子与表面光学（ＳＯ）声子耦合器，与体纵光学（ＬＯ）声子耦合弱的表面磁极化子的性质，采用线性组合算符和微扰法导出了极性晶体中表面磁极化子的有效哈密顿量。讨论了电子在反冲效应中发射和吸收不同波矢的声子之间相互作用对表面磁极化子有效质量的影响。     

Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process.      

楼宇安全门语音控制系统设计

详细介绍了语音识别芯片T6658A的结构、性能及工作原理 ,给出了基于T6658A设计的楼宇安全门语音识别系统的硬件电路和部分软件程序     

Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage characteristics of the SRAM cells. This allows us to explore the design space accurately with reliable process information at an early stage. By relying on supply voltage-dependent analysis, it is shown that the gate-leakage impact on the cell yield can be nonmonotonic and substantial even for nondefective devices. It is also shown that design optimizations such as increased operating voltages or shorter hierarchical bitline architecture can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield in terms of cell writability and stability. Threshold voltage variations to model random fluctuation effects are extrapolated from hardware results.     

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.