基于JPEG标准的图像压缩DCT变换

图像DCT变换是图像压缩的一项重要技术,如何准确、快速地进行图像压缩一直是国内外研究的热点.现研究了两种二维离散余弦变换(DCT)的方法.在DCT算法结构上利用了变换的可分离性和行列的可分解性,并采用行列分解的方法将二维DCT转换为2个串行的一维DCT实现.     

一种基于FPGA的二维DCT和IDCT的新算法

提出了一种新的二维DCT和IDCT的FPGA实现结构,采用行列快速算法将二维算法分解为两个一维算法实现,其中每个一维算法采用并行的流水线结构,每一个时钟处理8个数据,大大提高电路的数据吞吐率和运算速度。通过Modelsim仿真工具对该设计进行仿真,证明该算法的功能的正确性,进行一次8*8的分块二维DCT变换仅仅需要16个时钟,满足图像以及视频实时性的要求。     

基于FPGA的二维DCT变换的实现

二维离散余弦变换(DCT)在图像处理和视频编码中起重要的作用。以MPEG 2全I帧编码为背景,在现场可编程门阵列(FPGA)上实现8×8像素的二维DCT变换。算法首先把8×8像素的二维DCT变换化简成8次一维DCT变换加上适当的蝶形运算和顺序重排操作。试验表明,方案可以只用一个一维DCT模块实现输入采样率为74.25MHz的二维DCT变换。     

一种用于实时视频处理的高速二维DCT的电路设计和实现

绝大多数的国际图像和视频压缩标准都采用DCT(离散余弦变换)进行传输编码。本文介绍了一种基于矩阵分解算法的高速实时二维DCT处理器。为了满足视频处理的实时性，整个电路设计中广泛采用了流水线技术，文中详细介绍了二维DCT处理器的电路结构，最后给出了它的FPGA实现。     

二维DCT快速算法及FPGA实现

本文提出了一种二维OCT快速算法的FPGA实现结构,采用行列快速算法将二维DCT分解成两个一维DCT实现,其中一维DCT借鉴Loeffler DCT算法,采用并行的流水线结构,提高电路的数据吞吐率和运算速度,通过系数矩阵的简化和蝶形运算结构的等价减少乘法器的消耗,一维DCT核消耗16个乘法器.转置RAM采用8片双口RAM,一个时钟可以完成 8个数据读写.实验结果验证了二维DCT核设计的正确性,该电路结构消耗资源少,布线简单,功耗小,适合图像的实时处理.     

二维离散余弦变换及其逆变换的VLSI实现

针对适用于H.263及H.264视频压缩协议的编解码算法,二维离散余弦变换(DCT),及二维反离散余弦变换(IDCT),设计了ASIC高速电路,并完成了电路的FPGA模拟验证.在高速算法设计方面,利用一维变换来实现二维变换,通过对变换矩阵的特殊处理,使得一维变换中只含移位和加法运算;在电路设计方面,采用流水线结构并行处理数据,用寄存器堆实现矩阵的转置.对算法及电路设计的优化和改进,大大减少了完成一个矩阵二维正反变换所需要的周期数,提高了电路的吞吐率和运算速度.ASIC设计采用0.18 μm CMOS工艺,在最坏情况下,综合电路可达到的最高频率为250 MHz;FPGA模拟验证最高频率可达170 MHz.     

AVC/H.264整数离散余弦变换及反变换的结构设计

根据AVC/H.264标准中提出的整数离散余弦变换(DCT)及其反变换(iDCT)算法,旨在给出一种能够同时实现4×4,8×8 DCT/IdCT和Hadamard变换的设计方法.设计中充分利用DCT和iDCT的相似性和算法对称性,用高度并行结构来加快处理速度.采用一维DCT/iDCT单元复用的方式实现二维DCT/iDCT运算,同时提出实现设计的全定制实现方法,对全定制实现此设计进行初步布局规划.     

CCSDS中二维整数小波变换的FPGA实现方法

CCSDS空间图像压缩标准(CCSDS 122.0-B-1)的核心算法之一是三级二维小波变换,此变换适合用可编程逻辑电路实现。文章介绍了整数9/7小波变换的特点,提出了一种基于FPGA的二维变换快速实现结构,该方法利用FPGA内部Block RAM进行行暂存,实现了行列同时变换的效果,节省了内部寄存器资源,并获得了较高的数据吞吐率。在此基础上,文章还给出了两种适用于不同需求的多级变换架构,并通过仿真验证了其合理性。     

基于FPGA的H.264 DCT算法的硬件实现

二维离散余弦（DCT）在H.264视频编码中承担者信号从时域到频域变换的作用。在现场可编程逻辑门阵列（FPGA）上设计了高效的采用流水线结构的H.264DCT硬件电路。首先,把二维4×4DCT变换转换成二次一维DCT变换;其次,DCT变换之间加一个两端口的RAM,以实现数列的转置;最后,在顶层设计一个有限状态机控制整个流程。该设计采用较少的资源实现了较好的功能,获得了可靠的实验结果。     

二维DCT算法及其精简的VLSI设计

采用了快速算法,并通过矩阵的变化,得到了一维离散余弦变换(Discrete Cosine Transform,DCT)的一种快速实现,并由此提出一种精简的超大规模集成电路(Very-large-scale integration,VLSI)设计架构.使用了一维DCT的复用技术,带符号数的乘法器设计等技术,实现了二维DCT算法的精简的VLSI设计.实验结果表明,所设计的二维DCT设计有效,并能够获得非常精简的电路设计.     

Energy-Efficient 8-Point DCT Approximations: Theory and Hardware Architectures

Due to its remarkable energy compaction properties, the discrete cosine transform (DCT) is employed in a multitude of compression standards, such as JPEG and H.265/HEVC. Several low-complexity integer approximations for the DCT have been proposed for both 1D and 2D signal analyses. The increasing demand for low-complexity, energy-efficient methods requires algorithms with even lower computational costs. In this paper, new 8-point DCT approximations with very low arithmetic complexity are presented. The new transforms are proposed based on pruning state-of-the-art DCT approximations. The proposed algorithms were assessed in terms of arithmetic complexity, energy retention capability, and image compression performance. In addition, a metric combining performance and computational complexity measures was proposed. Results showed good performance and extremely low computational complexity. Introduced algorithms were mapped into systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology. All hardware-related metrics showed low resource consumption of the proposed pruned approximate transforms. The best proposed transform according to the introduced metric presents a reduction in power consumption of 21–25 %.     

AVS二维DCT变换的FPGA实现

以数字音视频编解码技术标准(Audio Video coding Standard,AVS)为背景,从离散余弦交换(Discrete Cosine Transform,DCT)的基本原理入手,研究了一种基于现场可编辑门阵列(Field Programmable Gate Array,FPGA)实现快速2D-DCT变换的方法.设计采用行列分解法把8×8的2D-DCT变换分解为2个1D-DCT,用移位求和的方法实现乘法器运算.同时,只用1个1D-DCT模块实现2D-DCT变换,节省了硬件资源,更提高了运算速度.最后,利用FPGA仿真工具MODELSIM SE 6.2b,完成了FPGA的实现与仿真结果.     

High performance architecture for unified forward and inverse transform of HEVC

High efficiency video coding (HEVC) transform algorithm for residual coding uses 2-dimensional (2D) 4×4 transforms with higher precision than H.264's 4×4 transforms, resulting in increased hardware complexity. In this paper, we present a shared architecture that can compute the 4×4 forward discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) of HEVC using a new mapping scheme in the video processor array structure. The architecture is implemented with only adders and shifts to an area-efficient design. The proposed architecture is synthesized using ISE14.7 and implemented using the BEE4 platform with the Virtex-6 FF1759 LX550T field programmable gate array (FPGA). The result shows that the video processor array structure achieves a maximum operation frequency of 165.2 MHz. The architecture and its implementation are presented in this paper to demonstrate its programmable and high performance.     

实时视频编码的二维DCT/IDCT的实现

用FPGA FLEX10130实现了二维离散余弦交换和逆变换（DCT／IDCT），结构设计采用行列分解法，乘法器采用移位求和的方法实现，并且采用流水线结构设计，提高处理核的性能，系统时钟达到33MHz，计算精度满足CCITT标准要求。     

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

In this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution.     

MPEG4编码器二维DCT变换的FPGA实现及优化

本文提出了一种适用于MPEG4视频编码系统的二维DCT的FPGA设计方案，该方案具有实时、高精度、易于FPGA实现的特点。在设计中，分别对DCT的算法及实现方法进行了分析和选择；在此基础上，对系统的结构进行了优化，提出了一种不同于传统二维DCT系统的新结构。最后对IDCT单元的运算精度进行了验证。     

FPGA实现AVS编码器P帧全过程

以数字音视频编码技术标准(Audio Video coding Standard,AVS)为依据,通过对该算法全过程的分析,并结合FPGA硬件平台的结构特点,设计了预测、DCT变换和反DCT变换、量化和反量化、熵编码的全过程。利用FPGA开发工具ISE10.1和仿真工具ModelSim SE 6.2b,并通过Xilinx公司xc5vlx110t-1ff1136平台验证,完成了AVS编码标准P帧从设计到实现的全过程。填补了AVS编码器P帧在FPGA上未实现的空白,同时促进了AVS在FPGA上的发展,并对AVS+和AVS 2发展起到关键性作用。