A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.     

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew

A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl mu/m /spl times/ 360 /spl mu/m) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%.     

Integrated transversal equalizers in high-speed fiber-optic systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-/spl mu/m SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-/spl mu/m multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10/sup -5/ to less than 10/sup -12/.     

A CMOS 0.25-/spl mu/m continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission

This paper presents a CMOS 0.25-/spl mu/m continuous-time 6-tap FIR filter that is used as a fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter delay line is realized with a second-order low-pass filter. Simulations show that the tap delay can be tuned from 100 ps to 300 ps while keeping a constant group delay within the bandwidth of 2.1 GHz and 800 MHz correspondingly. Experimental results show that the FIR filter can successfully recover a 1-Gb/s differential digital signal that has been transmitted over a 220-inch PCB trace which causes -31.48-dB attenuation at the symbol rate frequency of 1 GHz. The measured bit error rate after equalization is less than 10/sup -12/ over a 750-ps sampling range, compared to a 10/sup -2/ bit-error rate before equalization. Also presented are the measurement results comparing the horizontal and the vertical openings of the signals before and after equalization for PCB traces with different length. The chip dissipates 45 mW from a 2.5-V supply and occupies 0.33/spl times/0.27 mm/sup 2/ in a 0.25-/spl mu/m CMOS process.     

A 2-GHz CMOS image-reject receiver with LMS calibration

This paper describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-/spl mu/m CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and a third-order input intercept point of -17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 /spl times/ 1.84 mm/sup 2/.     

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.     

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

A 5-6.4 Gb/s transceiver, consisting of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO phase-locked loops (PLLs), and a clock recovery unit, was developed. The Tx has a five-tap pre-emphasis filter, and the Rx has an equalizer with an intersymbol interference (ISI) monitor. Monitoring the ISI enables fine adjustment of loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx compensate for transmission losses of up to 20 dB at 6.4 Gb/s, respectively. Both the Tx and Rx channels, including the PLLs, are 3.92 mm/sup 2/ in area. The transmitter dissipates 150 mW/channel at 6.4 Gb/s when compensating for a loss of 20 dB, and the receiver 90 mW/channel when compensating for the same loss.     

A 10 Gb/s BiCMOS adaptive cable equalizer

A 10 Gb/s adaptive equalizer IC using SiGe BiCMOS technology is described. The circuit consists of the combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI) for a variety of cable characteristics. The adaptive loop functions using a novel slope-detection circuit which has a characteristic that correlates closely with the amount of ISI. The chip occupies an area of 0.87 mm/spl times/0.81 mm and consumes a power of 350 mW with 3.3 V power supply. This adaptive equalizer is able to compensate for a cable loss up to 22dB at 5 GHz while maintaining a low bit-error rate.     

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

Ultrahigh-performance 8-GHz SiGe power HBT

This letter has demonstrated the state-of-the-art SiGe power heterojunction bipolar transistors (HBTs) operating at 8 GHz. In a common-base configuration, a continuous wave output power of 27.72 dBm with a concurrent power gain of 12.19 dB was measured at a peak power-added efficiency of 60.6% from a single SiGe HBT with a 3-/spl mu/m emitter finger stripe width and a 1340 /spl mu/m/sup 2/ total emitter area. The highest power-performance figure of merit (FOM) of 3.8/spl times/10/sup 5/ mW/spl middot/GHz/sup 2/ achieved from the device was resulted from using an optimized SiGe heterostructure and a compact device layout, which is made possible with a heavily doped base region.     

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.     

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.     

Efficient PDFA module using high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber

The highest reported single-pass gain coefficient of 0.36 dB/mW has been achieved using a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber, with a /spl Delta/n of 6.6%, a core diameter of 1.2 /spl mu/m and a transmission loss of 250 dB/km at 1.2 /spl mu/m. This fiber was used to construct an efficient PDFA module with a MOPA-LD. A small-signal net gain of 22.5 dB was achieved at 1.30 /spl mu/m with a pump power of 23m mW.     

1.58-/spl mu/m broad-band erbium-doped tellurite fiber amplifier

This paper describes the development of a 1.58-/spl mu/m broad-band and gain-flattened erbium-doped tellurite fiber amplifier (EDTFA). First, we compare the spectroscopic properties of various glasses including the stimulated emission cross sections of the Er/sup 3+4/ I/sub 13/2/ /sup 4/I/sub 15/2/ transition and the signal excited-state absorption (ESA) cross sections of the Er/sup 3+4/ I/sub 13/2/ - /sup 4/I/sub 9/2/ transition. We detail the amplification characteristics of a 1.58-/spl mu/m-band EDTFA designed for wavelength-division-multiplexing applications by comparing it with a 1.58-/spl mu/m-band erbium-doped silica fiber amplifier. Furthermore, we describe the 1.58-/spl mu/m-band gain-flattened EDTFA we developed using a fiber-Bragg-grating-type gain equalizer. We achieved a gain of 25.3 dB and a noise figure of less than 6 dB with a slight gain excursion of 0.6 dB over a wide wavelength range of 1561-1611 nm. The total output power of the EDTFA module was 20.4 dBm and its power conversion efficiency reached 32.8%.     

Room-temperature continuous-wave 1.55 /spl mu/m GaInNAsSb laser on GaAs

The first low-threshold 1.55 /spl mu/m lasers grown on GaAs are reported. Lasing at 1.55 /spl mu/m was observed from a 20/spl times/2400 /spl mu/m as-cleaved device with a room-temperature continuous-wave threshold current density of 579 A/cm/sup 2/, external efficiency of 41%, and 130 mW peak output power. The pulsed threshold current density was 550 A/cm/sup 2/ with >600 mW peak output power.     

35-dB gain Tm-doped ZBLYAN fiber amplifier operating at 1.65 /spl mu/m

We demonstrate the first high gain rare-earth-doped fiber amplifier operating at 1.65 /spl mu/m. It consists of ZBLYAN fiber with a Tm/sup 3+/-doped core and Tb/sup 3+/-doped cladding, pumped by 1.22 /spl mu/m laser diodes. It is possible to achieve efficient amplification with Tm/sup 3+/ ions if their amplified spontaneous emission (ASE) in the 1.75 to 2.0 /spl mu/m wavelength region is suppressed by doping Tb/sup 3+/ ions in the cladding. A two-stage-type fiber amplifier is constructed and a signal gain of 35 dB is achieved for a pump power of 140 mW. A gain over 25 dB is realized in the 1.65 /spl mu/m to 1.67 /spl mu/m wavelength region.     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.