Three-dimensional electrostatic effects of carbon nanotube transistors

We explore the three-dimensional (3-D) electrostatics of planar-gate carbon nanotube field-effect transistors (CNTFETs) using a self-consistent solution to the Poisson equation with equilibrium carrier statistics. We examine the effects of the gate insulator thickness and dielectric constant and the source/drain contact geometry on the electrostatics of bottom-gated (BG) and top-gated (TG) devices. We find that the electrostatic scaling length is mostly determined by the gate oxide thickness, not by the oxide dielectric constant. We also find that a high-k gate insulator does not necessarily improve short-channel immunity because it increases the coupling of both the gate and the source/drain contact to the channel. It also increases the parasitic coupling of the source/drain to the gate. Although both the width and the height of the source and drain contacts are important, we find that for the BG device, reducing the width of the 3-D contacts is more effective for improving short channel immunity than reducing the height. The TG device, however, is sensitive to both the width and height of the contact. We find that one-dimensional source and drain contacts promise the best short channel immunity. We also show that an optimized TG device with a thin gate oxide can provide near ideal subthreshold behavior. The results of this paper should provide useful guidance for designing high-performance CNTFETs.     

High-κ dielectrics and advanced channel concepts for Si MOSFET

With scaling of the gate length downward to increase speed and density, the gate dielectric thickness must also be reduced. However, this practice which has been in effect for many decades has reached a fundamental limitation because gate dielectric thicknesses in the range of tunneling have been reached with the SiO₂ dielectric layer for MOSFETs. Consequently, the gate dielectrics with higher dielectric constants, dubbed the “high-κ”, which allow scaling with much larger thicknesses have become active research and development topics. In this review technological issues associated with the likely high-κ materials which are under consideration as well as challenges, and solution to them, they bring about in the fabrication of Si MOSFET are discussed. Moreover, in order to squeeze more speed out of CMOS, channels for both n- and p-type MOSFET enhanced with appropriate strain and the concepts behind them are discussed succinctly. Finally, the longer term approach of replacing Si with other channel materials such as GaAs (InGaAs) for n-channel and Ge for p-channel along with technological developments of their preparation on Si and likely gate oxide developments are treated in some detail.     

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics

We have demonstrated a novel three-dimensional multibridge-channel metal-oxide-semiconductor field-effect transistor (MBCFET). This transistor was successfully fabricated using a conventional complementary metal-oxide-semiconductor process. We introduce the fabrication technologies and electrical characteristics of MBCFET in comparison with a conventional planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability than a planar MOSFET. This is due to the vertically stacked multibridge channels. The subthreshold swing of MBCFET is 61 mV/dec, which is almost an ideal value due to the thin body surrounded by gate. Based on a simulation result, we show that the MBCFET will have a large on-off state current ratio at short channel transistors.     

Electrostatics of nanowire transistors

The electrostatics of nanowire transistors are studied by solving the Poisson equation self-consistently with the equilibrium carrier statistics of the nanowire. For a one-dimensional, intrinsic nanowire channel, charge transfer from the metal contacts is important. We examine how the charge transfer depends on the insulator and the metal/semiconductor Schottky barrier height. We also show that charge density on the nanowire is a sensitive function of the contact geometry. For a nanowire transistor with large gate underlaps, charge transferred from bulk electrodes can effectively "dope" the intrinsic, ungated region and allow the transistor to operate. Reducing the gate oxide thickness and the source/drain contact size decreases the length by which the source/drain electric field penetrates into the channel, thereby, improving the transistor characteristics.     

Glucose Detection With a Commercial MOSFET Using a ZnO Nanowires Extended Gate

ZnO nanowires were grown on Ag wire with a diameter of ${sim}hbox{250} mu$ m and used in an electrochemical sensor. The enzyme glucose oxidase (GOD) was immobilized on the ZnO nanowires, and the Ag wire was connected directly to the gate of a MOSFET. Upon exposure to glucose (1– $hbox{100} mu$M), the electrochemical response from the GOD induced a stable measurable voltage change on the gate leading to a strong modulation of the current through the MOSFET. For a sensor with uniform ZnO nanowires functionalized with GOD, a fast response time of less than 100 ms was demonstrated. The effect of the uniformity of the ZnO nanowires on the sensing property was also investigated. The extended-gate arrangement facilitated glucose detection in small sample volumes, and made it possible to demonstrate the present sensor concept using a standard low-threshold MOSFET. The extended-gate MOSFET sensor approach demonstrates the possibility and potential of the use of nanostructures coupled to standard electronic components for biosensing applications.      

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.     

Significant aspects of minority-carrier injection in dynamic-threshold SOI MOSFET at low-temperature

This paper demonstrates significant aspects of low-temperature minority-carrier injection in n-channel dynamic-threshold (DT) MOSFET having various silicon-on-insulator (SOI) layer thicknesses. Drain current vs. gate voltage and gate current vs. gate voltage characteristics are evaluated at temperatures ranging from 300 K to 30 K, and minority-carrier injection is characterized. Impacts of temperature, channel length, and silicon-on-insulator layer thickness on opposite drain current behavior are discussed by examining transconductance behavior.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

Interfacial charge transfer in nanoscale polymer transistors

Interfacial charge transfer plays an essential role in establishing the relative alignment of the metal Fermi level and the energy bands of organic semiconductors. While the details remain elusive in many systems, this charge transfer has been inferred in a number of photoemission experiments. We present electronic transport measurements in very short channel (L < 100 nm) transistors made from poly(3-hexylthiophene) (P3HT). As channel length is reduced, the evolution of the contact resistance and the zero gate voltage conductance are consistent with such charge transfer. Short channel conduction in devices with Pt contacts is greatly enhanced compared to analogous devices with Au contacts, consistent with charge transfer expectations. Alternating current scanning tunneling microscopy (ACSTM) provides further evidence that holes are transferred from Pt into P3HT, while much less charge transfer takes place at the Au/P3HT interface. This article is published with open access at Springerlink.com     

Work function characterization of electroactive materials using an /sup E/MOSFET

Materials with redox properties have been widely used in sensing applications. Understanding the redox properties of these materials is an important issue. In order to investigate the redox properties, there are several methods, such as using the Kelvin probe and a conductivity sensor, or using other well-known electrochemical techniques. In this paper, we introduce another possibility to characterize redox materials by investigating their work function using an electrolyte metal-oxide semiconductor field effect transistor (/sup E/MOSFET) device, in which the studied redox material is applied as gate electrode. In the /sup E/MOSFET, the conductivity of the channel is modulated by the work function of the studied material. The change in the work function of a redox material due to electrically and chemically induced processes will be shown by an example of the /sup E/MOSFET having a potassium ferric ferrocyanide gate.     

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F² cell array     

Optimum power-saving method for power MOSFET width of DC/DC converters

An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC-DC converters. By implementing a one-cycle buck DC-DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ~92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ~16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC-DC converters     

Scaling down of organic thin film transistors: short channel effects and channel length-dependent field effect mobility

Organic thin film transistors with P3HT (poly-3-hexylthiophene) as active semiconducting layer, channel lengths from 0.3 to 20 μm, and gate oxide thicknesses from 15 to 170 nm have been successfully fabricated on Si substrates. The measurement results show that the channel length over oxide thickness ratio should be large enough (i.e., the vertical electric field should be at least 10 times higher than the lateral electric filed) in order to suppress the short channel effects of transistors. The field effect mobility of long channel devices (L ≥ 5 μm) is about an order of magnitude larger than small channel devices (L from 0.3 to 2.5 μm), which could be attributed to the more severe contact resistance effects between organic materials and metal contacts for devices with smaller dimensions.     

Sub-threshold study of undoped trigate nFinFET

Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate voltage dependent. In our work we have studied the sub-threshold behavior of undoped triple gate MOSFETs (FinFETs) using a thermionic transport model. We have analyzed the conductance data of such devices, and from this, we have been able to determine the evolution of both the active cross-section area of the channel and the barrier height as a function of the gate voltage. The result of our experiments shows good agreement with tight binding simulations and with analytical results. This confirms the validity of the use of our thermionic approach to study transport in sub-micrometer size FinFET devices and not only in micrometer size samples specially made for characterizations.     

The impact of structural parameters on the electrical characteristics of silicon nano wire transistor based on non equilibrium Green's function

In this paper we have used a fully ballistic quantum mechanical transport approach to analyse electrical characteristics of rectangular silicon nanowire field effect transistor in 7 nm gate length. We have investigated the impact of structural parameters of Gate all around Silicon nano wire transistor (GAA-SNWT) on its electrical characteristics in subthreshold regime. In particular we have shown the effect of increasing the Source/Drain and channel length (L(S), L(D) and L(Ch)) on short channel effects as well as change in body thickness and independent back gate voltage. We also investigate the effect of increasing the gate underlap on the electrical characteristics and on the switching speed of device. We show that if the Lun is increased the gate capacitance and DIBL will reduce while the I(ON)/I(OFF) ratio is increased.     

Realizing lateral wrap-gated nanowire FETs: controlling gate length with chemistry rather than lithography

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the subthreshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 and 4 K, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.     

SOI MOSFET with an insulator region (IR-SOI): A novel device for reliable nanoscale CMOS circuits

Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high-K dielectric HfO₂ as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO₂ considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices.     

Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed

Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si channels by controlled solid-state conversion of Ge/Si NWs to NiSixGe y alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious short-channel effects present in lithographically defined sub-100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drain-source bias of 0.5 V yield transconductance values of 78 and 91 microS, respectively, and maximum on-currents of 121 and 152 microA. The scaled transconductance and on-current values for a gate and bias voltage window of 0.5 V were 6.2 mS/microm and 2.1 mA/microm, respectively, for the 40 nm device and exceed the best reported values for planar Si and NW p-type FETs. In addition, analysis of the intrinsic switching delay shows that terahertz intrinsic operation speed is possible when channel length is reduced to 70 nm and that an intrinsic delay of 0.5 ps is achievable in our 40 nm device. Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub-100 nm Ge/Si NWFETs with integrated high-kappa gate dielectric operate near the ballistic limit.     

Simulation based performance comparison of transistors designed using standard photolithographic and coarse printing design specifications

In this work a simulation based comparative study of organic field effect transistors designed using standard lithographic and printing designs is presented. The device simulations were performed using two-dimensional drift-diffusion equations with a Poole-Frenkel field dependent mobility model. Both photolithographic and coarse printing transistor designs employed common materials such as 150 nm thick pentacene, 150 nm thick parylene gate insulator, gold source-drain electrodes and aluminum gate electrodes. The major differences between the two fabrication specifications are the minimum source/drain line width and the transistor channel length. The typical specifications for the minimum line width and channel length were 2 μm and 5 μm for photolithography and 25 μm and 20 μm for coarse printing techniques, respectively. The gate, source, and drain capacitances and channel on-resistances at various channel lengths and gate overlaps have been extracted and presented specifically for both process schemes. Due to increased channel length and gate-source/drain overlap of printed electrodes relative to lithographic design, the resulting on-resistance and capacitances for coarse printing are significantly higher. These results demonstrate a substantial operating frequency reduction for printing design relative to photolithographic design. For the tested materials and designs it is shown that the cut-off frequency for the photolithographic process was 400 kHz but decreased to a much lower 26 kHz for the coarse printing process. Since printing technology uses various other materials, which typically have less performance than the ones used for this simulation, the actual printed device might have even lower performance than predicted here.