A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of \(53\,\hbox {V}/\mu \hbox {s}\) with a phase margin of \(78^{\circ }\) .     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using \(0.18\,\upmu \hbox {m}\) CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of \(-6\)  dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of \(-60, -110, -52\) and \(-64\)  dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.     

Anisotropic Thermopower of the Kondo Insulator \hbox {CeRu}_4\hbox {Sn}_6

The intermetallic compound \(\hbox {CeRu}_4\hbox {Sn}_6\) has been tentatively classified as Kondo insulator. This class of material, especially non-cubic representatives, is not yet fully understood. Here we report thermopower measurements on single-crystalline \(\hbox {CeRu}_4\hbox {Sn}_6\) between 2 K and 650 K, along the main crystallographic directions. Large positive thermopower is observed in the directions along which the hybridization is strong and a Kondo insulating gap forms. A negative contribution to the thermopower dominates for the crystallographic \(c\) axis where hybridization is weak and metallicity prevails.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

A Novel Design of Low Power Rectenna for Wireless Sensor and RFID Applications

In this paper, an efficient microstrip rectenna operating on ISM band with high harmonic rejection is presented. By using rotated E-shaped strip in the radiating patch, a new resonance at lower frequencies (2.4 GHz) can be achieved. Also by embedding cutting a rectangular slot with protruded interdigital strip inside the slot in the feed line a frequency band-stop performance can be achieved. The proposed structure has a major advantage in high harmonic rejection. The rectenna with integrated monopole antenna can eliminate the need for an low pass filter placed between the antenna and the diode as well as produce higher output power, with maximum conversion efficiency of 74 % using a 1 K \(\Omega \) load resistor at a power density of \(0.3\,\hbox {mW/cm}^{2}\) .     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

Soft X-ray Absorption and Photoemission Spectroscopy Study of Cobalt-Based Thermoelectric Oxides: \hbox{Ca}_3\hbox{Co}_4\hbox{O}_9, \hbox{Ca}_3\hbox{Co}_2\hbox{O}_6, and \hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}

The electronic structures of Co-based potential thermoelectric (TE) oxides, including $\hbox{Ca}_3\hbox{Co}_4\hbox{O}_9$ and $\hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}$ (y = 8 + δ) single crystals and polycrystalline $\hbox{Ca}_3\hbox{Co}_2\hbox{O}_6$ , have been investigated by employing soft x-ray absorption spectroscopy (XAS) and photoemission spectroscopy (PES). Co 2p XAS measurements show that Co ions are nearly trivalent ( $\hbox{Co}^{3+}$ ) in all of these Co-based TE oxides with a small mixture of $\hbox{Co}^{4+}$ ions in $\hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}$ . Valence-band PES and O 1s XAS measurements show that the occupied Co 3d states are located at the top of the valence bands and that the lowest unoccupied states have the primarily Co 3d character, respectively. These findings suggest the importance of the Co 3d electronic structures in determining TE properties of these Co-based oxides.     

Voltage-mode multifunction filter with mutually independent Q and \omega _0 control feature using VDDDAs

The paper focuses on the application possibilities of the newly presented voltage differencing active building block called voltage differencing differential difference amplifier. Using this active element, a multifunction frequency filter is designed featuring the possibility of mutually independent control of quality factor Q and characteristic frequency \(\omega _0\) by means of active elements. The structure of the filter is based on the idea of the Akerberg-Mossberg (AM) filter, i.e. the integrators in the structure are always realized only by two active elements. This fact results in better phase compensation for the filter. Compared to the AM opamp based filter, the newly proposed structure features high-impedance inputs, low-impedance output, and all basic frequency responses. The performance of the proposed structure has been verified by SPICE simulations using the TSMC \(0.18\,\upmu \hbox {m}\) level-7 SCN018 CMOS process parameters with \(\pm 0.9\,\hbox {V}\) supply voltage.     

Nanovoid Formation and Dynamics in He+-Implanted Nanocrystalline Silicon

Helium implantation in single crystal silicon is known to lead, after a proper thermal treatment, to the formation of voids with diameters ranging between 10 nm and 30 nm. Formation of voids is governed by the coalescence of vacancies created by implantation, initially trapping helium atoms. At high temperatures ( \({\ge}700^{\circ }\hbox {C}\) ), helium leaves the nanobubbles and outdiffuses, while the now empty voids grow in size and eventually change their shape to form tetrakaidecahedra (Wulff construction). In this communication, we report how He⁺ implantation in heavily boron-doped nanocrystalline silicon shows a completely different dynamics. Annealing at \(500^{\circ }\hbox {C}\) leads to the formation of large voids, located around grain boundaries, along with a large number of nanovoids with an average diameter of 2–4 nm and an estimated density of \(3\times 10^{17}\,\hbox {cm}^{-3}\) distributed throughout the grains. Annealing at higher temperature (up to \(1000^{\circ }\hbox {C}\) ) also induces a decrease of the void size with a change in their density, finally accounting to \(2\times 10^{18}\,\hbox {cm}^{-3}\) . The high temperature annealing also causes vacancy evaporation down to a depth of 80–100 nm from the outer surface. The possibility of obtaining a stable, uniform distribution of nanometer-sized voids is of major relevance as a novel tool for phonon and electron engineering in thermoelectric materials.     

Design and modeling of high-resolution multibit log-domain \Delta \Sigma modulators

Log-domain Delta-Sigma ( $\Delta \Sigma$ ) modulators are attractive for implementing analog-to-digital (A/D) converters (ADCs) targeting low-power low-voltage applications. Previously reported log-domain $\Delta \Sigma$ modulators were limited to 1-bit quantization and, hence, could not benefit from the advantages associated with multibit quantization (namely, reduced in-band quantization noise, and increased modulator stability). Unlike classical $\Delta \Sigma$ modulators, directly extending a log-domain $\Delta \Sigma$ modulator with a 1-bit quantizer to a log-domain $\Delta \Sigma$ modulator with a multibit quantizer is challenging, in terms of CMOS circuit implementation. Additionally, the realization of log-domain $\Delta \Sigma$ modulators targeting high-resolution applications necessitates minimization of distortion and noise in the log-domain loop-filter. This paper discusses the challenges of multibit quantization and digital-to-analog (D/A) conversion in the log-domain, and presents a novel multibit log-domain $\Delta \Sigma$ modulator, practical for CMOS implementation. SIMULINK models of log-domain $\Delta \Sigma$ modulator circuits are proposed, and the effects of various circuit non-idealities are investigated, including the effects of log-domain compression–expansion mismatch. Furthermore, this paper proposes novel low-distortion log-domain analog blocks suitable for high-resolution analog-to-digital (A/D) conversion applications. Circuit simulation results of a proposed third-order 3-bit class AB log-domain $\Delta \Sigma$ loop-filter demonstrate 10.4-bit signal-to-noise-and-distortion-ratio (SNDR) over a 10 kHz bandwidth with a $0.84\,V_{pp}$ differential signal input, while operating from a 0.8 V supply and consuming a total power of $35.5\,\upmu \hbox {W}.$      

Performance Analysis of Microwave Radio Refractivity on Radio Field Strength and Radio Horizon Distance Over Akure,Nigeria

Surface radio refractivity studies are being carried out in Akure, \((7.15^{\circ }\hbox {N}, 5.12^{\circ }\hbox {E})\) South-Western Nigeria, by in-situ measurement of atmospheric pressure, temperature, and relative humidity using Wireless Weather Station (Integrated Sensor Suit, ISS). Five years of measurement (January, 2007–December, 2011) were used to compute the surface radio refractivity and its diurnal, daily, seasonal and yearly variations are analyzed. The results were then used to compute radio horizon distance \((\hbox {R}_\mathrm{DH})\) and examine the field strength (FSV) variability. Results obtained show that the surface radio refractivity, \(\hbox {N}_\mathrm{s}\) , varies with the time of the day as well as the seasons of the year. High values of \(\hbox {N}_\mathrm{s}\) were recorded in the morning and evening hours while the values were minima around 1,500 h local time. An average value of surface radio refractivity of 364.74 N-units was obtained for this location. The annual maximum mean of FSV is 15.24 dB and the minimum is 2.20 dB. This implies that the output of a receiving antenna in Akure may generally be subject to variations not less than 2 dB in a year, but can be as high as 15 dB.     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

Electronic Structure and Thermoelectric Properties of Pseudoquaternary \hbox{Mg}_{2}\hbox{Si}_{1-x-y}\hbox{Sn}_{x}\hbox{Ge}_{y}-Based Materials

A theoretical study is presented on complex pseudoternary Bi-doped \(\hbox{Mg}_{2}\hbox{Si}_{1-x-y}\hbox{Sn}_{x}\hbox{Ge}_{y}\) materials, which have recently been revealed to reach high thermoelectric figures of merit (ZT) of ～1.4. Morphological characterization by scanning electron microscopy and energy-dispersive x-ray spectroscopy indicated that the investigated samples were multiphase and that the alloy with nominal composition \(\hbox{Mg}_{2}\hbox{Si}_{0.55}\hbox{Sn}_{0.4}\hbox{Ge}_{0.05}\) contained three phases: \(\hbox{Mg}_{2}\hbox{Si}_{0.35}\hbox{Sn}_{0.6}\hbox{Ge}_{0.05}\) (Sn-rich phase), \(\hbox{Mg}_{2}\hbox{Si}_{0.65}\hbox{Sn}_{0.3}\hbox{Ge}_{0.05}\) (Si-rich phase), and \(\hbox{Mg}_{2}\hbox{Si}_{0.15}\hbox{Sn}_{0.5}\hbox{Ge}_{0.35}\) (Ge-rich phase). The electronic structure of all these phases was calculated in the framework of the fully charge self-consistent Korringa–Kohn–Rostoker method with the coherent potential approximation (KKR-CPA) to treat chemical disorder. Electron transport coefficients such as the electrical conductivity, thermopower, and the electronic part of the thermal conductivity were studied by combining the KKR-CPA technique with Boltzmann transport theory. The two-dimensional (2D) plots (as a function of electron carrier concentration and temperature), computed for the thermopower and power factor, well support the large thermoelectric efficiency detected experimentally. Finally, employing the experimental value of the lattice thermal conductivity as an adjustable parameter, it is shown that ZT ≈ 1.4 can be reached for an optimized Bi content near T ≈ 900 K in case of the nominal composition as well as the Sn-rich phase. The question of the effect of disorder on the convergence of the conduction bands and thus the electron transport properties is addressed through detailed examination of the Fermi surfaces.     

Method for Designing Efficient Mixed Radix Multipliers

The multiplication of two signed inputs, \(A {\times } B\) , can be accelerated by using the iterative Booth algorithm. Although high radix multipliers require summing a smaller number of partial products, and consume less power, its performance is restricted by the generation of the required hard multiples of B ( \(\pm \phi B\) terms). Mixed radix architectures are presented herein as a method to exploit the use of several radices. In order to implement efficient multipliers, we propose to overlap the computation of the \(\pm \phi B\) terms for higher radices with the addition of the partial products associated to lower radices. Two approaches are presented which have different advantages, namely a combinatory design and a synchronous design. The best solutions for the combinatory mixed radix multiplier for \(64\times 64\) bits require \(8.78\) and \(6.55~\%\) less area and delay in comparison to its counterpart radix-4 multiplier, whereas the synchronous solution for \(64\times 64\) bits is almost \(4{\times }\) smaller in comparison with the combinatory solution, although at the cost of about \(5.3{\times }\) slowdown. Moreover, we propose to extend this technique to further improve the multipliers for residue number systems. Experimental results demonstrate that best proposed modulo \(2^{n}{-}1\) and \(2^{n}{+}1\) multiplier designs for the same width, \(64{\times }64\) bits, provide an Area-Delay-Product similar for the case of the combinatory approach and \(20~\%\) reduction for the synchronous design, when compared to their respective counterpart radix-4 solutions.     

9.9 V ASK Demodulator Using Differential Shaper for High-Impedance Electrode

This paper proposes a 9.9 V ASK demodulator for the high-impedance micro-stimulating electrode. In order to receive the 9.9 V ASK modulated signal, a cascoded HV rectifier is utilized to rectify the HV (high voltage) ASK modulated signal and generates a miniature rectified signal with voltage \(<\) 3.3 V, such that the reliability problem can be avoided. Besides, a differential generator and a differential shaper are employed to amplify the miniature rectified signal. The theoretical analysis and the condition are given to guarantee the proposed ASK demodulator functionally working in all process and temperature corners. Besides, the aspect ratios of the MOS transistors can be easily found according to the analysis results. The simulation and measurement results are also given to verify the analysis results. Thus, the HV modulated signal could be demodulated easily without any off-chip step-down circuit, boost circuit and HV process required. The proposed design is carried out using TSMC 0.35  \(\upmu \) m CMOS process. The core area is \(109.515 \times 56.925\,\upmu {\text {m}}^2\) . The maximum data rate is measured to be 1.25 Mbps with the carrier frequency of 12.5 MHz.