Nanometer mixed-signal system-on-a-chip design

A mixed-signal system-on-a-chip (SoC) design methodology and the supporting CAD tools are presented. A known tools set is identified for illustration purposes and some alternative tools can equally accomplish the task.     

Multidisciplinary Electronic Package Design and Optimization Methodology Based on Genetic Algorithm

A new multidisciplinary design and optimization methodology in electronics packaging is presented. A genetic algorithm combined with multidisciplinary design and multiphysics analysis tools are used to optimize key design parameters. This methodology is developed to improve the electronic package design process by performing multidisciplinary design and optimization at an early design stage. To demonstrate its capability, the methodology is applied to a ball grid array (BGA) package design. Multidisciplinary criteria including thermal, thermal strain, electrical, electromagnetic leakage, and cost are optimized simultaneously. A simplified routability analysis criterion is used as a constraint. The genetic algorithm is used for systematic design optimization. The present methodology can be applied to electronics product design at various packaging levels.     

Mixed-signal IC design guide to enhance substrate noise immunity in bulk silicon technology

Predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve substrate parasitic voltage and substrate propagation are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. A typical study shows the possibility of such a method and measurements finally demonstrate its efficiency.     

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-μm operational transconductance amplifiers having equal 50-μA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz^1/2, and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes. David M. Binkley (S’81, M’82, SM’93) joined the University of North Carolina at Charlotte in 2000 as an associate professor in the electrical and computer engineering department. Dr. Binkley and his students are researching analog design and testing methodologies including micropower, low-noise analog CMOS design for neural implants and radiation hardened, deep space applications. Dr. Binkley was a cofounder and vice president of integrated circuit development at Concorde Microsystems and senior scientist at CTI PET Systems where he designed both discrete and integrated CMOS electronics for positron emission tomography (PET) medical imaging systems. Concorde and CTI are currently part of Siemens Medical Solutions. Dr. Binkley received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville. He is the author of over 60 papers in analog circuit design and instrumentation and holds five U.S. patents. Dr. Binkley is currently writing the book, Analog CMOS Design, Tradeoffs and Optimization, for John Wiley and Sons with planned publication in 2006. Benjamin J. Blalock (S’, M’) received his B.S. degree in electrical engineering from the University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He joined the Department of Electrical and Computer Engineering at Mississippi State University in 1996 and the University of Tennessee in 2001. His current research focus includes mixed-signal/mixed-voltage circuit design for systems-on-a-chip in SOI technology, analog IC design for extreme environments, multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, and bio-microelectronics. He has over 25 publications in the field of analog IC design and has contributed to The Circuits and Filters Handbook. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems, Inc. James M. Rochelle (M’84) received the B.S., M.S., and Ph.D. degrees in Electrical engineering from the University of Tennessee, Knoxville. From 1965 to 1982 he was with the Instrumentation and Controls Division of the Oak Ridge National Laboratory. From 1982 to 2001, he was Associate Professor of Electrical and Computer Engineering at the University of Tennessee, Knoxville teaching and conducting research in integrated circuit device modeling and mixed-signal integrated circuit design. In 2001 he retired from academia and is presently an emeritus associate professor and vice president of ASIC development at Concorde Microsystems, Inc., now part of Siemens Medical Solutions located in Knoxville, Tennessee. His current research interests are mixed-signal ASIC's for medical imaging readout electronics and micropower battery-powered devices.     

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain. Michael Chan received his bachelor degrees in Electrical Engineering and Computer Science from the University of Queensland in 2003. He is currently working towards his PhD at the same institution. His research interests include the design of high-speed clock and data recovery systems, and high speed phase locked loops. Adam Postula received the M.S. degree in electrical engineering from the Warsaw University of Technology, Poland, in 1974 and the Ph.D. degree in signal processing from the Poznan University of Technology, Poland, in 1981. He was an Electronic System Designer with ABB Sweden and a Researcher with the Royal Institute of Technology, Stockholm, Sweden, from 1983 to 1992. He led the development of high-level synthesis tools at the Swedish Institute of Microelectronics and was engaged in VHDL standardization in Europe. Since 1995, he has been a Senior Lecturer in the Department of Computer Science and Electrical Engineering, University of Queensland, Brisbane, Australia. His research interests include digital system design methodology, synthesis of digital systems, specialized processor architectures, and VLSI signal processing. Ding Yong received his PhD from University of London in electrical engineering in 1991. He was with National University of Singapore as a research scientist working in industrial research projects on data channel and servo-system for CD technology. In 1995, he joined VLSI design group of Western Digital as a principle engineer, where he was engaged in the IC design of Hard Disk Controller and CD-ROM Decoder and Controller. From 2000, he has been leading a mixed-signal design group as design manager and chief architect with Nano Silicon responsible for development of high-speed serial data transmission IPs. Lech Jóźwiak is an Associate Professor, Head of the Section of Digital Circuits and Formal Methods, at the Faculty of Electrical Engineering, Eindhoven University of Technology, The Netherlands. He received his M.Sc. and Ph.D. degrees in Electronics from the Warsaw University of Technology, Warsaw, Poland, in 1976 and 1982, respectively. From 1979 to 1986, he was a chief of two R&D teams in the Research Institute of Computers in Warsaw, and consultant to the United Nations Industrial Development Organization and industry. From 1986, he works mainly in the Netherlands, but also from time to time in USA, Canada, Australia, Belgium and Poland, combining advanced theoretical research with professional engineering practice and collaborating with industry, academia and governments. He is an author of a new information-driven approach to digital circuit synthesis, and new theories and methodologies of information relationships and measures, general decomposition and quality-driven design that have a considerable practical importance. He is also a creator of a number of practical products in the fields of application-specific (embedded) systems and EDA tools. His research interests include system, circuit, information and design theories and technologies, decision and optimization methodology, artificial intelligence, circuit and system design and EDA, re-configurable and massively parallel high-performance systems, embedded systems, and system dependability, analysis and validation. He is an author of more than 130 journal and conference papers and of some book chapters. He is a Director of EUROMICRO, co-founder and Steering Committee Chair of the EUROMICRO Symposium on Digital System Design, VIP in the IEEE International Symposium on Quality Electronic Design, program committee member of many other conferences, member of IEEE, EDAA, and of the Advisory Committee of the IEE Professional Network Embedded and Real-Time System Engineering. He is an advisor to the industry, Ministry of Economy and Commission of the European Communities in the fields of microelectronics, information technology, technology development and transfer, and SMEs.     

Efficient methods for modelling substrate coupling in mixed-signalintegrated circuits

A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits     

Efficient synthesis methodology for optimal inverter-based transimpedance amplifiers

In this paper, we present a new synthesis methodology that facilitates the design automation of maximum bandwidth transimpedance amplifier (TIA) for optical communications under the constraint of a specific bit error rate. Our synthesis methodology is based on newly developed models that characterize the input referred noise and bandwidth. Our technique provides the optimal parameters of the transimpedance amplifier for maximizing the bandwidth. These optimal parameters are mapped to equivalent circuit parameters to achieve the optimal sizing of the TIA. Our methodology is characterized by its very fast design convergence as well as better results compared to conventional design techniques. We applied our synthesis methodology in designing a TIA for optical interconnect systems using the 0.25μm and 0.18μm CMOS technologies. Mohamed Elnozahi is a PhD student in the Rice Automated Nanoscale Design Group at the department of Electrical and Computer Engineering, Rice University. His research interests include the design and design automation of analog and mixed-signal circuits. Yehia Massoud received the B.Sc. and M.Sc. degrees (with honors) from Cairo University, Egypt. He received the PhD degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology, MIT, Cambridge, in 1999. He is the founding director of the Rice Automated Nanoscale Design Group at Rice University, where he is currently an Assistant Professor in the departments of Electrical and Computer Engineering and Computer Science at Rice University, Houston, Texas, USA. Before joining Rice University in 2003, he was a member of the Technical Staff at the Advanced Technology Group at Synopsys Inc., Mountain View, California, USA, from 1999 to 2003. His research interests include the modeling and design automation of mixedsignal integrated systems as well as alternatives for on-chip and chip-to-chip communication in future nanoscale systems. He is a recipient of the National Science Foundation CAREER Award for 2004.     

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta–sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Mixing it

By definition, automotive electronic systems are embedded mixed-signal systems because they feature multiple analogue sensors and analogue actuators under digital control. For years, traditional oscilloscopes have been the primary tool-of-choice among automotive electronic system design engineers to measure the quality of both analogue and digital signals. But traditional analogue and digital oscilloscopes have many limitations, including a lack of triggering functions for complex serial events and a limited number of input channels for acquisition. However, a new class of measurement tool called the mixed signal oscilloscope (MSO) has stepped into that breach, presenting its own debugging methodology     

Interoperability Verification in ISO 18000-7 Active RFID Systems: Experimental Setup and Results

Interoperability in an RFID system conforming to ISO 18000-7 standard is defined as the ability of any commercial interrogator to communicate with any commercial tag. A possibility that conformance verification in the physical communication layer between active tags and interrogators (readers) does not satisfy the interoperability property is established. Challenging the traditional or matrix test to verify interoperability, a novel methodology to verify interoperability for active RFID systems in particular and all communication systems following a command-reply protocol in general is introduced in a prior publication. In this article, the methodology is experimentally implemented using industry standard laboratory equipment and automation tools to develop a fully automated interoperability test suite. The automated test system design considerations, challenges and results are discussed in detail. For a particular equipment, the NI-5671 Radio Frequency Signal generator, the maximum number of samples that can be tested for different parameters of the physical communication layers are provided. The equipment limitations are discussed to provide the reader with guidelines to experiment with, and a reference to evaluate the resolution (one measure of the accuracy of the test) of different equipment. The different parameters considered in the test and their interactions in determining the interoperability property are recorded.     

Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current

In this paper we have investigated a unified and simultaneous fault detection method for mixed-signal integrated circuits. The method is based on the analysis of the power-supply current through the circuit under test. The analysis has been done paying attention to the dynamic behaviour of the power-supply current, in order to avoid measurement problems related to the large amount of quiescent current drop across many analog blocks.The analysis of the dynamic power-supply current entails certain problems related to the complexity of the measurement process, especially those due to the high speed of the current transients. These problems have been addressed by considering a design for test procedure based on the use of built-in dynamic current sensors.The goal of the design for test methodology proposed is to represent the Iddt through the mixed-signal IC under test by a digital signature. The paper presents some advantages of this approach such as a good tolerance to cross-talk noise and the need for only a conventional digital tester on the complete mixed-signal IC for fault detection. The analysis is illustrated with some test results.     

Using top-down CAD tools for mixed analog/digital ASICs: a practical design case

A mixed analog/digital ASIC from a real satellite application (a radiation detector front-end) has been designed, simulated and processed according to a hierarchical top-down design methodology. CAD tools (commercial and academic) have been used as much as possible. The top-down methodology is discussed and illustrated by going through the different steps of the ASIC design. At each level the differnt choices and tradeoffs are briefly discussed and practical difficulties of top-down design are pointed out. One of the most important problems in top-down mixed-signal ASIC design—modeling and verification—is highlighted and discussed in detail.research associate of the BeIgian National Fund of Scientific Research     

人工智能驱动下的雷达发展思考

智能化雷达在现有雷达技术的基础上,利用人工智能技术及先进的信号处理技术,赋予雷达自主的感知、决策、学习、执行和协作能力,从而提升其对复杂环境的感知能力及对目标的探测能力。文中针对人工智能驱动下的雷达技术发展问题,首先,分析了人工智能技术在雷达系统中的应用现状;然后,结合人工智能技术以及雷达信号处理技术的发展,从大数据、多平台协同、多源信息融合、人机混合增强以及自主智能感知等方面对人工智能驱动下的雷达发展趋势进行探讨;最后,结合人工智能驱动下的雷达发展趋势,提出了有针对性的发展建议,并进行总结。     

Speeding DSP algorithm design

The boom in the use of systems based on digital signal processing (DSP) is rivalled only by the swiftness with which their technology changes. No sooner do engineers master the latest development than a still newer one emerges. It's the same with design tools; it never seems quite possible for the users to catch up. Designing DSP based systems, therefore, remains a challenging and multidisciplinary task. More often than not, unfortunately, there is a gap between the algorithm development and implementation phases of a DSP design project. Therefore, DSP engineers are turning in droves toward a methodology that integrates the design of DSP algorithms with the later stages of development and implementation. Called “accelerated DSP design” (ADD), the methodology makes use of high level algorithm simulation and rapid prototyping (on off the shelf DSP boards)-both offline and in real time environments-to achieve its goals. The tools it uses allow early validation of algorithms and evaluation of tradeoffs, increasing the designer's confidence that a particular design will meet its requirements     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

Current criticalities and innovation perspectives in flash memory design automation

With reference to technological, architectural, and market considerations, the specific areas of design methodology and automation in flash memory design are analyzed in this paper. For each of the activities identified as critical, we show the design process key constraints and specifications, which drive the change in methodology, tools, and flows. We go through a brief survey of the solutions adopted in the recent past as well as the new emerging areas of intervention. The analysis covers: 1) design methodology, floorplanning, full-custom layout design and Rtl2Layout automation integration; 2) analog-digital mixed full-chip simulation and architectural exploration; 3) statistical analog circuital simulation; 4) mixed-signal design to test approaches; and 5) IC and package design integration.     

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.