一种新颖的W-CDMA主同步信道匹配滤波器

W-CDMA系统中,各基站之间是异步时序关系.为了快速识别基站,3GPP协议引入了三步同步的小区搜索算法.第一步对主同步信道的搜索是极其重要的.采用传统的匹配滤波器结构占用的硬件资源非常庞大.主同步信道是由广义分层Golay序列构成的,根据其构造特性,我们提出一种新颖的广义分层Golay匹配滤波器(简称GHGMF).理论分析证明该结构大幅度降低了硬件实现的复杂度,对于工程应用具有重要价值.     

基于DFT滤波器组的多载波调制系统设计

采用DFT滤波器组来代替OFDM系统中的IDFT/DFT模块,形成基于滤波器组的收发器。设计适于多经衰落信道的DFT滤波器组收发器。其均衡与OFDM系统一样,是在接收端采用单抽头的均衡器。实验采用随机多径信道,仿真结果表明所提出的滤波器组收发器可以获得较好的频谱特性,以及较满意的SIR（信号与干扰比值）。     

一种基于MMF-FRM的低复杂度信道化接收机结构

为实现时域重叠信号的全概率接收和跨信道信号重构，降低窄过渡带信道化结构的复杂度，提出一种基于调制屏蔽滤波器频率响应屏蔽（Modulation Masking Filter Frequency Response Masking, MMF-FRM）技术的信道化接收机结构.通过对原型屏蔽滤波器进行调制得到两个分支屏蔽滤波器，给出了基于MMF-FRM的窄过渡带滤波器设计方法 .推导出一种基于MMF-FRM的低复杂度信道化接收机结构，该信道化结构解决了多相分解受FRM(Frequency Response Masking)滤波器组限制的问题，并分析了该结构的有限字长性质和纹波系数.用Xilinx System Generator进行了硬件实现与仿真，在采样速率为1 GHz，信道数为8的条件下，提出的信道化接收机结构比多相信道化结构节省74.1%的乘法器资源，比FRM信道化结构节省13.5%的乘法器资源.     

LTE系统中PUSCH关键模块的FPGA实现

提出一种第三代合作伙伴(3GPP)长期演进(LTE)上行共享信道中传输预编码的实现方案,即基于现场可编程门阵列(FPGA)的多种混合基离散傅里叶变换/离散傅里叶逆变换(DFT/IDFT)处理器.这种DFT/IDFT处理器根据不同的输入数据长度进行动态配置,使硬件资源得到共享,处理速度及数据精度满足LTE系统测试要求.采用Verilog HDL语言在Xilinx公司的Virtex-5系列FPGA芯片内成功对该处理器模块进行了验证,并对其进行了优化.     

认知NC-OFDM系统一种改进的信道估计

介绍了认知无线电NC-OFDM系统中的信道估计技术,着重分析了随机插入导频模式和迭代IDFT变换域降噪方法。通过引入转换分解算法,对迭代IDFT变换域降噪方法进行改进,改进的信道估计算法与迭代IDFT变换域降噪方法有相同的估计性能,但改进的信道估计算法运算量少,估计器复杂度低,提高了硬件资源的利用,具有实用性。     

W-CDMA系统中辅同步信道捕获的改进

W-CDMA系统中,各基站之间是异步时序关系。为了快速识别基站,3GPP协议引入了三步同步的小区搜索算法。第二步对辅同步信道的搜索是极其重要的。采用传统的匹配滤波器组结构运算复杂度比较大。该文分析了辅同步信道的结构,根据其构造特性提出了部分快速哈达玛变换(PFHT)的快速算法。理论分析证明该算法减少了接近70％的运算量。同时,针对辅同步信道的RS码表搜索,提出了一种分布式子图搜索算法,与穷举搜索相比,大幅度降低了复杂度。经过这两方面的改进,使辅同步信道捕获的硬件设计复杂度大大降低,对于工程应用具有重要价值。     

一种改进的基于NRA的信道估计器

提出了一种改进的基于噪声减小算法(NRA)的信道估计方法，该方法不仅适用于采样时钟与信道脉冲响应同步的条件下，同样也适用于非同步的条件下，而且该方法在降低噪声影响方面相比于DFT—IDFT传输域滤波具有较低的计算复杂度。仿真表明，该算法具有良好的性能。     

MIMO-OFDM系统中一种改进的信道估计方法

信道的准确估计是提高MIMO-OFDM系统性能的关键.在最优导频时域信道估计的基础上,提出了一种较低复杂度的改进算法,利用时变信道的自回归(AR)模型构造卡尔曼滤波器对估计出的时域信道响应进行滤波,提高信道时域响应的估计精度.仿真结果表明,在慢时变信道环境下,改进方法可以进一步提高信道估计的精度,同时保持了较低的复杂度.     

群信号信道化技术实现方法的仿真与分析

针对群信号中有用子信道信号检测和解调难度较大的问题,通过分析均匀数字滤波器组分析器的基本型,提出了将多相结构和奇偶分路应用于群信号信道化技术的方法。仿真结果表明,这两种方法都有效降低了算法复杂度,而奇偶分路法进一步提高了算法的运行效率,目前已通过硬件实现。     

面向工业自组织网络混响衰落信道模拟的双目标优化方法

传统信道模拟方法针对室外信道提出，难以满足工业自组织网络设备研制中混响信道连续冲激响应的模拟需求。通过使用较低阶的无限冲激响应数字滤波器（IIR）逼近工业混响信道连续冲激响应特征，提出了同时纳入滤波器阶数与响应误差的双目标优化目标函数，从而在IIR滤波器复杂度和模拟精度之间寻求平衡。仿真结果表明，与现有的平衡截断法和多项式放等方案相比，所提算法得到的滤波器复杂度更低，且模拟精度更高。     

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.     

Software radio issues in cellular base stations

The use of the “software radio” concept in cellular applications is a topic of widespread interest. Two key issues in the implementation of software radios are the development of optimal receivers that require the minimum number of bits in the wide-band analog-to-digital converter (ADC) and efficient channelizers that extract individual channels from the digitized wide-band signal. In this paper, both of these issues are studied in detail for cellular base stations. A computationally efficient wide-band channelizer is presented. This channelizer is closely related to the discrete Fourier transform filter bank used in transmultiplexers. It is shown that the complexity of the proposed channelizer is significantly less (2-50×) than the complexity of conventional channelizers. An optimal receiver that explicitly takes into account the effect of the quantization noise of the wide-band ADC is also derived. The analysis of the ADC noise provides guidelines for specifying wide-band ADC for use in cellular applications. The development of the channelizer and the optimal receiver yield important insights into the implementation of cellular software radios. All of the key results of this paper are applied to a detailed example based on the Digital Advanced Mobile Phone System (D-AMPS, IS-54/IS-136) cellular standard. The bit-error rate (BER) performance simulations of a D-AMPS wide band receiver is presented as a part of this example     

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.     

高效非均匀数字信道化及信号重建技术

针对宽带接收机接收信号多,且信号在频谱上呈现非均匀分布的情况,提出了基于多相离散傅里叶变换(DFT)滤波器组和信号重建的高效非均匀数字信道化的设计方法.该数字信道化结构由分析和综合两部分组成,采用同一组原型滤波器系数,通过对原型低通滤波器的优化设计提高其带外衰减性能,以利用平行结构正交镜像滤波器组重建信号.与常用的并行...     

A Low Complexity Reconfigurable Non-uniform Filter Bank for Channelization in Multi-standard Wireless Communication Receivers

In a typical multi-standard wireless communication receiver, the channelizer must have the capability of extracting multiple channels (frequency bands) of distinct bandwidths corresponding to different communication standards. The channelizer operates at the highest sampling rate in the digital front end of receiver and hence power efficient low complex architecture is required for cost-effective implementation of channelizer. Reconfigurability is another key requirement in the channelizer to support different communication standards. In this paper, we propose a low complexity reconfigurable filter bank (FB) channelizer based on coefficient decimation, interpolation and frequency masking techniques. The proposed FB architecture is capable of extracting channels of distinct (non-uniform) bandwidths from the wideband input signal. Design example shows that the proposed FB offers multiplier complexity reduction of 83% over Per-Channel (PC) approach and 60% over Modulated Perfect Reconstruction FB. The proposed FB when designed as a uniform FB (subbands of equal bandwidths), offers a complexity reduction of 20% over Discrete Fourier Transform FB (DFTFB) and 57% over Goertzel Filter Bank. Furthermore, the proposed FB has an added advantage of dynamic reconfigurability over these FBs. The proposed FB is implemented on Xilinx Virtex 2v3000ff1152-4 FPGA with 16 bit precision. The PC approach and DFTFB are also implemented on the same FPGA with 14 bit precision. The implementation results shows an average slice reduction of 29.14% and power reduction of 46.84% over PC approach, 14.39% and 2.67% over DFTFB.     

Reconfigurable channel filtering and digital down conversion in optimal CSD space for software defined radio

Software defined radio (SDR) is a platform for using the same hardware to support multiple wireless communication standards. The channelizer in the SDR is used to separate the channels from the wideband signal. The features required for using the same hardware to switch between different standards are reconfigurability and low complexity. To achieve this, we use a variable bandwidth filter (VBF) with facility for the reduction and enhancement of the bandwidth, without changing the filter coefficients. This paper proposes an optimal and multiplier-less implementation of a baseband channel filter for supporting the bandwidth requirements of various wireless communication standards. This paper also discusses the concept for using it as a multi-band SDR channelizer for the direct conversion of signals from a wideband input to the baseband signal without using an intermediate stage. Frequency response masking (FRM) filter with continuous coefficients is designed and modified harmony search algorithm is used for finding the optimal canonic signed digit representation for the multiplier-less implementation. This reduces the complexity and power consumption. The VBF with the optimized FRM filter is evaluated for the selectable bandwidths starting from 1.25 to 8 MHz, which covers the bandwidth requirements of a wide range of wireless communication standards.     

一种迭代正弦频率估计硬件实现研究

 本文提出了一种基于迭代算法的八通道滤波器组单频正弦信号频率估计方法,该算法的基本思想是利用频域重叠的多通道滤波器来实现大的频率估计范围,同时提高单通道内的信噪比;还对滤波抽取后的数据进行迭代,这样即使采用运算量最小的不加权线性预测算法也能实现高精度测频,并采用FPGA实现了该算法,最后数值仿真结果证实所提算法的优异性能.     

A Low Complexity Reconfigurable Multi-stage Channel Filter Architecture for Resource-Constrained Software Radio Handsets

Software defined radio (SDR) is emerging as a powerful platform for future generation cellular systems, due to its capability to operate conforming to multiple mobile radio standards. Channelizer in an SDR operates at the highest sampling rate and hence a low complexity design is needed for the most computationally intensive part of the SDR receiver. The channel filters in the channelizer extracts radio channels of varying bandwidths, corresponding to various communication standards from the wideband input signal. An architecture for implementing low complexity, low power and reconfigurable channel filter for the SDR mobile handsets, based on multi-stage frequency response masking (FRM) is proposed in this paper. The proposed architecture is unique in a way that it is able to effectively exploit the redundancy in multi-stage realization by utilizing the common masking filters and also capable of extracting varying bandwidth channels. Design examples show that the proposed architecture offers 47.5% complexity reduction and 18.1% power reduction over single-stage FRM approach.     

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer

A software-defined radio (SDR) channelizer extracts narrowband channels from the wideband signal. The impulse response of this filter is required to change with the desired channel to be extracted from the wideband input. A reconfigurable filter is used instead of fixed filters to implement the channelizer in a resource-constrained environment. In this paper, we present a throughput-scalable reconfigurable architecture for SDR channelizer. The proposed structure processes a block of L input samples and produces one block of L outputs in every clock cycle. The register complexity of the proposed structure is independent of throughput, whereas multiplier and adder complexity increases proportionately. A significant number of registers are saved when the proposed structure is implemented for larger filter-length and higher block-sizes. Theoretical estimates show that the proposed structure for the block-size 8 and filter-length 32 involves 256 extra multipliers and 105 extra adders against 6912 MUXes, 8 less registers than those of the existing similar structure, and it offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure of block-size 8 and filter-length 32 involves 41 % less area-delay product and 22 % less energy per sample than those of the existing structure and offers nearly 6 times higher sampling rate than the other. At the normalized sampling rate, the proposed structure for filter-length 16 consumes 18 % and 22 % less power than the existing structure for block-sizes 4 and 8, respectively.