Packaging effects on reliability of Cu/low-k interconnects

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.     

Interlevel dielectric failures in copper/low-k structures

Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.     

Moisture influence on porous low-k reliability

In this paper, the impact of moisture on the reliability of porous low-k materials has been investigated. It was found that moisture uptake is higher for more porous SiOC low-k materials, and its presence inside the low-k has a strong impact on the dielectric reliability. It has been demonstrated that by eliminating moisture, the leakage current can be significantly decreased; in addition, higher breakdown electric fields and longer dielectric lifetimes can be achieved. Therefore, integration of porous low-k materials requires maximum attention to prevent moisture uptake at each step during integration; in addition, the passivation layers need to be perfectly hermetic in order to maintain good dielectric reliability.     

Interface reliability assessments for copper/low-k products

Multiple new materials are being adopted by the semiconductor industry at a rapid rate for both semiconductor devices and packages. These advances are driving significant investigation into the impact of these materials on device and package reliability. Active investigation is focused on the impact of back-end-of-line (BEOL) processing on Cu/low-k reliability. This paper discusses Cu/low-k BEOL interfacial reliability issues and relates key items from the assembly process and packaging viewpoint that should be managed in order to prevent adverse assembly impact on BEOL interfacial reliability. Reliability failure mechanisms discussed include interface diffusion-controlled events such as the well-known example of Cu electromigration (EM), as well as stress-migration voiding. Interface defectivity impact on dielectric breakdown and leakage is discussed. Lastly, assessments of assembly impact on these Cu/low-k interfacial concerns are highlighted.     

Power-Substrate Static Thermal Characterization Based on a Test Chip

Thermal simulation is, nowadays, a basic tool to predict temperature distributions and heat fluxes of complex packages and modules. These variables are of main importance in high-power assemblies to analyze and predict their reliability limits. Nevertheless, the simulation results can be inaccurate due to the uncertainty of the values of the physical parameters involved in the models, as it is the case for the thermal conductivity of the dielectric layers (ceramics and composites) of the main families of power substrates [direct copper bonded (DCB) and insulated metal substrate (IMS)]. We propose a methodology for the in situ determination of these thermal conductivities under true operation conditions. Three test assemblies based on a thermal test chip and different types of power substrates (two IMS and one DCB) have been characterized in order to deduce their thermal resistance. Three-dimensional numerical models of the assemblies have also been developed. Thereby, the thermal conductivity of the critical layers is derived by minimizing the error between the experimental and the simulated thermal resistances. From the subsequent simulation results, the vertical temperature distributions are analyzed in order to predict the thermal stresses of the different layers inside the substrates.      

High Frequency Attenuation in Transmission Class Solid Dielectric Cable

High frequency attenuation in shielded distribution cable is well understood; however, this cannot be said of transmission class solid dielectric cable, which has a more complicated structure, including additional semiconducting ldquobeddingrdquo layers and a moisture barrier in the form of metal tape or corrugated metallic sheath. These additional elements cause new sources of high frequency loss relative to solid dielectric distribution cable. We report measurements of high frequency loss for transmission class solid dielectric cable with a corrugated copper sheath and for cable with a metal tape moisture barrier and wire screen (concentric neutral). Analytic approximations have been developed for the various sources of high frequency loss in these cable structures, and the analytic approximations have been checked using finite element analysis. Good agreement has been achieved between the computed and measured loss.     

Stress-induced electromigration backflow effect in copper interconnects

The electromigration threshold in copper interconnect is reported in this paper. The critical product (jL)/sub c/ is first determined for copper oxide interconnects with temperature ranging from 250/spl deg/C to 350/spl deg/C from package-level experiments. It is shown that the product does not significantly change in this temperature range. Then, (jL)/sub c/ was extracted for copper low-k dielectric (k=2.8) interconnects at 350/spl deg/C. A larger value than that for oxide dielectric was found. Finally, a correlation between the n values from Black's model and with jL conditions was established for both dielectrics.     

Flip-chip packaging using micromachined conductive polymer bumpsand alignment pedestals for MOEMS

Using flip-chip bonding techniques with micromachined conductive polymer bumps and passive alignment techniques with electroplated side alignment pedestal bumps, a prototype microoptoelectromechanical systems (MOEMS) structure for optical input/output (I/O) couplers has been designed, fabricated and characterized. A top MOEMS substrate has through holes, contact metal pads, and side alignment pedestals with electroplated NiFe to align GaAs metal-semiconductor-metals (MSMs). Conductive polymer bumps have been formed on contact metal pads of GaAs MSMs using thick photoresist bump-holes as molding patterns. A diced GaAs photodetectors die with micromachined conductive polymer bumps was aligned to the side alignment pedestals and flip-chip bonded onto the substrate. This conductive polymer flip-chip bonding technique allowed a very low contact resistance (~10 mΩ), a lower bonding temperature (~170°C), and simple processing steps. The GaAs MSM photodetectors flip-chip mounted on the top of OE-MCM substrate showed a low dark current of about 10 nA and a high responsivity of 0.33 A/W     

Simulation of thin-TFETs using transition metal dichalcogenides: effect of material parameters,gate dielectric on electrostatic device performance

In recent years, significant of scientific research effort has focused on the investigation of transition metal dichalcogenides (TMDC) and other two-dimensional (2D) materials like graphene or boron nitride. Theoretical investigation on the physical aspects of these materials has revealed a whole new range of exciting applications due to wide tunability in electronic and optoelectronic properties. Besides theoretical exploration, these materials have been successfully implemented in electronic and optoelectronic devices with promising results. In this work, we have investigated the effect of monolayer TMDC materials and monolayer TMDC alloys on the performance of thin tunneling field-effect transistors or thin-TFETs. These are promising electronic devices that can achieve steep switching characteristics. We have used the self-consistent determination of the conduction and valence band levels in the device and a simplified model of interlayer tunneling current reported in recent literature that treats scattering semiclassically and incorporates the energy broadening effect using a Gaussian approximation . We have also explored the effect of gate dielectric material variation, interlayer dielectric variation, top gate metal workfunction on the performance of the device. Our study shows that proper choice of material in the top and bottom layers, optimization of materials used as gate and interlayer dielectric are necessary to extract the full potential of these devices. The electron affinity and bandgap of the TMDCs used in different layers effectively control the threshold voltage and current in the device. As seen from our simulation, interlayer materials with high dielectric constant can degrade subthreshold device performance, increase threshold voltage, whereas lowering interlayer thickness could increase device ‘on’ current at the expense of degraded subthreshold performance.     

基于金属表面等离子体激元的光调制器研究

采用模式展开法研究了具有周期性空气孔亚波长阵列的“金属-介质-金属”结构对电磁波的透射特性。由于金属表面等离子体激元具有增强透射效应,使得该结构对电磁波有高通滤波的效果。当两层金属间介质的折射率发生变化时,该结构的透射谱中的峰值频率也随之移动。利用该特性,设计了光调制器结构,通过在该结构的上、下层金属加栽电压,即可改变中间层介质的折射率,从而对正入射的光波起到调制作用。研究表明,当介质折射率变化0．5％时,该调制器的调制深度达到88％。     

Application of TOFSIMS for Contamination Issues in the Assembly World

Within the assembly world, problems related to package contamination, which stem from material sourcing and assembly process excursions, can impact product reliability. From the reliability perspective, it is essential to achieve integrity at all internal interfaces in the flip-chip, wire-bond, and novel mixed technology packages. In many instances, both organic and low-level ionic contaminants have resulted in interface delamination, metal migration, microcracking, etc., which leads to a premature failure of products either in reliability tests or in the field. Several examples of failure analysis relating to package contamination in the assembly world and the effectiveness of time-of-flight secondary ion mass spectroscopy in isolating and understanding failures are highlighted in this paper.     

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform.The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 m lines/space widths and 40 m pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive.This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.     

Investigation of interfaces with analytical tools

This paper focuses on advancements in three areas of analyzing interfaces, namely, acoustic microscopy for detecting damage to closely spaced interfaces, thermal imaging to detect damage and degradation of thermal interface materials and laser spallation, a relatively new concept to understand the strength of interfaces. Acoustic microscopy has been used widely in the semiconductor assembly and package area to detect delamination, cracks and voids in the package, but the resolution in the axial direction has always been a limitation of the technique. Recent advancements in acoustic waveform analysis has now allowed for detection and resolution of closely spaced interfaces such as layers within the die. Thermal imaging using infrared (IR) thermography has long been used for detection of hot spots in the die or package. With recent advancements in very high-speed IR cameras, improved pixel resolution, and sophisticated software programming, the kinetics of heat flow can now be imaged and analyzed to reveal damage or degradation of interfaces that are critical to heat transfer. The technique has been demonstrated to be useful to understand defects and degradation of thermal interface materials used to conduct heat away from the device. Laser spallation is a method that uses a short duration laser pulse to cause fracture at the weakest interface and has the ability to measure the adhesion strength of the interface. The advantage of this technique is that it can be used for fully processed die or wafers and even on packaged devices. The technique has been used to understand interfaces in devices with copper metallization and low-k dielectrics.     

Effect of Insulating Barriers in Arc Flash Testing

Low-voltage arc flash testing has been conducted using the standard IEEE 1584 test procedure but modified so that the electrode tips are terminated in an insulating barrier instead of in the open air. The barrier prevents downward arc motion, has a stabilizing effect on the arcs, and produces a strong horizontal plasma cloud flow. It also produces shorter arc lengths, higher arcing currents and higher maximum incident energy density, when compared with the standard arrangement presently used. The erosion of the copper electrodes is much higher when a barrier is used, which causes a much larger quantity of copper spray to be directed toward the outside of the box. Similar results can be observed when vertical conductors are terminated in real industrial components. The effect of the barrier and the source X/R on arc sustainability at 208 V has also been studied. The barrier test arrangement is believed to be more representative of real-world equipment. It is proposed that an arrangement like this should be incorporated into future revisions of the IEEE 1584 testing standard.      

Electric field reduction due to charge accumulation in adielectric-covered electrode system

Outlines for increased insulation performance of an air gap through the use of dielectric coatings are given. Theoretically, it is shown that the homogeneous electric field in a plane-parallel electrode system can be reduced if the electrodes are covered with a thick dielectric coating. Free charges will be affected by the electric field between the electrodes and are deposited at the dielectric surfaces. As a consequence, a counteracting electric field component results, which accordingly causes a reduction of the total electric field in the air gap and an enhancement of the field in the dielectric layers, i.e. the electric field is forced into the dielectric coatings by the charges. This effect has important implications in HV engineering. Introductory experiments supporting the idea have been carried out with promising results. It was confirmed that the withstand voltage of a plane-parallel electrode geometry with an open air gap, for dc as well as unipolar impulse voltage, could be increased considerably if the electrodes were covered with thick polymeric layers. Charge formation at the electrode surfaces as well as in the air gap is believed to be responsible for this effect. In today's insulation systems, this is known to work only for time-independent electric fields, i.e. generally dc voltages. Further experimental work is required and will be performed in order to scrutinize thoroughly and clarify the phenomenon, its capabilities and limitations     

Hot-Electron-Induced Degradation in BCB- and SiN-Passivated Al0.25Ga0.75As/In0.2Ga0.8As PHEMTs

In this paper, the hot-electron-induced degradation in Al_0.25Ga_0.75As/In_0.2Ga_0.8As pseudomorphic high-electron-mobility transistors passivated by low-k benzocyclobutene (BCB) has been investigated. Compared to the more commonly used silicon nitride (SiN), BCB has a lower dielectric constant and loss tangent and is becoming popular for passivation. However, its influence on the device hot-electron reliability has not been extensively studied so far. This paper examines the changes in the device dc drain-current, transconductance, and OFF-state breakdown voltages before and after hot-electron stress. For comparison purposes, the results for a device passivated using SiN have been included. The dominant mechanism that is responsible for the degradation in each technology has also been proposed and explained.     

基于功率型LED散热技术的研究

散热制约了LED功率的进一步提高。本文在分析功率LED受热效应影响的基础上,从改进LED结构角度来解决散热问题。芯片采用倒装焊结构,可降低热阻,提高散热能力,对倒装焊结构的热能扩散途径进行了阐述,指出采用导热性能优良的封装材料是提高散热效率的重要途径。并对密封材料,键合材料,散热基板对散热的影响作了详细的分析,最后介绍了采用热沉散热的最新进展,并提出了今后的研究方向。     

Investigation of dielectric/metal bilayer sidewall diffusion barrier for Cu/porous ultra-low-k interconnects

A dielectric/metal bilayer structure of a-SiC:H/Ta was integrated and investigated for application as a sidewall diffusion barrier in a Cu/porous ultra-low-k interconnect structure. Different dielectric/metal bilayer thicknesses were investigated. The electrical tests and physical analyses indicate that this a-SiC:H/Ta bilayer structure is a more efficient sidewall diffusion barrier than the conventional physical vapor deposited (PVD) multistack TaN/Ta metal barrier. With a similar total sidewall barrier thickness, an even better barrier integrity and reliability can be achieved by using a thicker a-SiC:H layer and a correspondingly thinner Ta barrier. This achievement is mostly attributed to the surface modification and sealing of the porous ultra-low-k surface by the a-SiC:H layer. Thus, the scenario of the barrier failure due to defects in the Ta (or TaN) barrier layer directly deposited on rough porous ultra-low-k material is avoided. Bias-temperature stress (BTS) and time-to-failure (TTF) studies indicate the Copper penetration through the sidewall barrier into the porous dielectric was the dominating failure mechanism in the conventional PVD TaN/Ta barrier and bilayer barrier of thinner a-SiC:H (14 /spl Aring/) and thicker Ta (71 /spl Aring/) layers, although the latter enhanced the lifetime of interconnect structures considerably. The bilayer barrier consisting of a thicker a-SiC:H (60 /spl Aring/) and correspondingly thinner Ta (53 /spl Aring/) layers was more robust to protect the sidewall region so that this sidewall Cu diffusion induced failure mechanism was no longer found in Cu/porous ultra-low-k interconnect structures even after thermal stress at 200/spl deg/C for 120 h.     

Multilayer High-Gradient Insulators

High voltage systems operated in vacuum require insulating materials to maintain spacing between conductors held at different potentials, and may be used to maintain a nonconductive vacuum boundary. Traditional vacuum insulators generally consist of a single material, but insulating structures composed of alternating layers of dielectric and metal can also be built. These "high-gradient insulators" have been experimentally shown to withstand higher voltage gradients than comparable conventional insulators. As a result, they have application to a wide range of high-voltage vacuum systems where compact size is important. This paper describes ongoing research on these structures, as well as the current theoretical understanding driving this work.     

A new polyimide film for VLSI and its electrical characterization

Multilevel structures consisting of alternating metal and dielectric layers are necessary to achieve interconnection in high density or VLSI (very large scale integration) circuits using either MOS or bipolar technology. Polyimide is one of the excellent high temperature heat-resistant polymers in organic materials and has good planarization capability and electrical insulating properties. In this work, following the synthesis of DAPDS (4,4'-bis (3-aminophenoxy)diphenyl sulfone), by nucleophilic aromatic substitution of 4,4'-dichlorodiphenyl sulfone with m-aminophenol, DAPDS/pyromellitic dianhydride based soluble and processable fully imidized polyimide was synthesized successfully by using solution imidization technique. Using this specific polyimide, a metal-polyimide-silicon MIS (metal polyimide silicon) structure was manufactured. Electrical properties of the MIS capacitance have been examined. The planarizing and patterning characteristics and electrical characteristics such as current vs. voltage, breakdown field strength, permittivity and capacitance vs. voltage for quasi-static and high frequency measurements are discussed. The results are compared with conventional dielectric films used in integrated circuit fabrication