倒装芯片封装器件开封方法研究

对倒装芯片封装(Flip-Chip Package)器件开封技术进行了研究。总结了倒装芯片封装的类型、结构和封装材料；从理论上证明了倒装芯片封装器件开封的可能,并找出了限制开封的制约因素；提出了一种倒装芯片封装器件开封方法,通过X射线检查、镶嵌、磨抛和酸刻蚀的综合应用,突破了限制这类器件开封的因素,并证明了该方法的适用性；给出了建议的试验条件,并展示了开封效果。     

超级CSP——一种晶圆片级封装

研究了圆片级芯片尺寸封装.使用再分布技术的圆片级封装制作了倒装芯片面阵列.如果用下填充技术,在再分布层里和焊结处的热疲劳应力可以减小,使倒装芯片组装获得大的可靠性.     

超级CSP—一种晶圆片级封装

研究了圆片级芯片尺寸封装。使用再分布技术的圆片级封装制作了倒装芯片面阵列。如果用下填充技术，在再分布层里和焊结处的热疲劳应力可以减小，使倒装芯片组装获得大的可靠性。     

超级CSP—一种晶圆片级封装

在本文里,研究了圆片级芯片尺寸封装,使用再分布技术的圆片级封装制作了倒装芯片面阵列。如果用下填充技术,在再分布层里和焊结处的热疲劳应力可以减小,使倒装芯片组装获得大的可靠性。     

层叠封装(PoP)组装的挑战

本文提出了一种大批量层叠封装(PoP)组装方法,这种方法利用了倒装芯片组装中已有的电子封装技术。本文讨论了多个挑战和考虑因素。许多文章[1、2、3]详细介绍了这一新型封装的要求和实例。本文将演示怎样使用自动贴装机和倒装芯片组装使用的选项,堆叠和组装这些模块。为适应底部CSP较大的球体尺寸及使用焊膏和助焊剂,对上述技术必须进行某些改动。堆叠要求的精度要高于标准SMT贴装。某些现有的SMT贴装机可以进行改进,采用相应的改动精确地高速贴装堆叠的CSP。这种方法在成本上非常有竞争力。我们还将他细分析部分测试工具的设计问题。这些测试工具是为了深入考察工艺和组装问题而研制的。     

堆叠(PoP)组装的挑战

提出了一种大批量堆叠(PoP)组装方法,这种方法利用了倒装芯片组装中已有的电子封装技术,讨论了多个挑战和考虑因素;演示了怎样使用自动贴装机和倒装芯片组装使用的选项、堆叠和组装这些模块。为适应底部CSP较大的球体尺寸及使用焊膏和助焊剂,必须进行某些改动,堆叠要求的精度要高于标准SMT贴装,某些现有的SMT贴装机可以进行改进,采用相应的改动精确地高速贴装堆叠的CSP,这种方法在成本上非常有竞争力。     

堆叠（PoP）组装的挑战

本文提出了一种大批量堆叠（PoP）组装方法，这种方法利用了倒装芯片组装中已有的电子封装技术。本文讨论了多个挑战和考虑因素。许多文章详细介绍了这一新型封装的要求和实例。本文将演示怎样使用自动贴装机和倒装芯片组装使用的选项，堆叠和组装这些模块。为适应底部CSP较大的球体尺寸及使用焊膏和助焊剂，必须进行某些改动。堆叠要求的精度要高于标准SMT贴装。某些现有的SMT贴装机可以进行改进，采用相应的改动精确地高速贴装堆叠的CSP。这种方法在成本上非常有竞争力。我们还将回顾为进一步考察工艺和组装问题而研制的部分测试工具的设计。     

堆叠（POP）组装的挑战

本文提出了一种大批量堆叠（PoP）组装方法，这种方法利用了倒装芯片组装中已有的电子封装技术。本文讨论了多个挑战和考虑因素。 许多文章详细介绍了这一新型封装的要求和实例。本文将演示怎样使用自动贴装机和倒装芯片组装使用的选项，堆叠和组装这些模块。为适应底部BCSP较大的球体尺寸及使用焊膏和助焊剂，必须进行某些改动。堆叠要求的精度要高于标准SMT贴装。某些现有的SMT贴装机可以进行改进，采用相应的改动精确地高速贴装堆叠的CSP。这种方法在成本上非常有竞争力。 我们还将回顾为进一步考察工艺和组装问题而研制的部分测试工具的设计。     

倒装片封装引领风骚 2003年大展身手

2000年起,英特尔的Slot1架构全部转为Socket370,封装则采用Flip Chip PGA封装技术;其845芯片组目前也以倒装片技术进行封装。其后,英特尔的主要竞争者AMD也开始相继采用倒装片封装。在移动通讯的应用上,如索尼爱立信的蓝牙模块,也已经跨入倒装片封装的领域。2002年封装大厂的技术发展主力,多着重在倒装片技术能量的布局,在产品特性需求的驱动下,预计倒装片技术的应用将在2003年开始起飞。     

倒装芯片键合技术发展现状与展望

我国集成电路发展十二五规划中提到,大力发展先进封装和测试技术,推进高密度堆叠型三维封装产品的进程,支持封装工艺技术升级和产能扩充。阐述了先进封装技术中的倒装芯片键合工艺现状及发展趋势,以及国际主流倒装设备发展及国内应用现状,重点介绍了北京中电科装备有限公司的倒装机产品。国产电子装备厂商应认清回流焊倒装芯片键合设备市场发展,缩短倒装设备产品开发周期和推向市场的时间,奠定国产电子先进封装设备产业化基础;同时抓紧研发细间距铜柱凸点倒装和热压焊接技术,迎接热压倒装芯片工艺及其设备的挑战。     

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension.This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability.     

Development of a mathematical model for thermal-compression bonding of the COG packaging process using NCA

In this decade, many new techniques have been introduced into the integrated circuit (IC) packaging industry. Packaging technology used in liquid crystal displays (LCDs) has requirements related to critical issues such as high density interconnects, thinner packaging size, and environmental safety. Driver IC chips are directly attached to LCD panels using flip chip technology with adhesives in the so called chip on glass (COG) packaging processes. To investigate the dependence of the bonding force on the bump deformation during packaging, this study established a mathematical model to analyze COG packaging processes with non-conductive adhesives (NCAs). The plastic deformation of the bumps and the NCA flow between the chip and substrate are taken into account in this model. With this model, the contact resistance and the gap height after bonding can be estimated for different bonding force.     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一。对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素。针对不同清洗方式及参数的清洗效果进行对比,并研究助焊剂残留对底部填充效果的影响,以对倒装焊清洗技术进行优化。试验结果表明,利用预清洗(≥3 min)、正式清洗(≥3 min)、蒸汽漂洗(≥3 min)、真空干燥(≥4 min)的真空汽相清洗流程可充分洗净倒装焊芯片与基板细微间距中的助焊剂并且无清洗液残留,从而保证了底部填充胶的快速流动及完全固化,填充胶空洞率可达5%以下。     

Reliability of MOS LSl circuits

MOS LSI circuits share many of the reliability problem associated with discrete semiconductors and medium-scale integrated circuits. However, because of the added complexity, larger chip size, and higher densities of MOS LSI circuits, different approaches are needed. A close working relationship between the designer, manufacturer, and user-the reliability triangle--is needed to generate the manufacturing controls, testing methods, and reliability assessment procedures and to optimize the performance and reliability of the MOS LSI circuits. Using this approach, the MOS LSI circuit, having more functions per external connection, can provide a more reliable system than one of equal complexity, based on discrete devices or less complex integrated circuits. Specific areas of reliability such as pattern sensitivity, manufacturing controls, assembly, packaging, and electrical testing have also been discussed.     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

Genetic algorithms for defect detection of flip chips

Flip chip packaging technology is widely used in high density assembly and superior performance devices. The solder joints are sandwiched between dies and substrates, leading to the defects optically opaque. Defect inspection of flip chips become more difficult. In this paper, a nondestructive detection method was presented. Ultrasonic excitations were forced on the surface of the flip chips and the raw vibration signals were measured by a laser scanning vibrometer. Eleven time domain features and twenty-four frequency domain features were extracted for analysis. After that, the genetic algorithm was introduced for feature selection and the back propagation network was adopted for classification and recognition. The flip chips were divided into three categories: good flip chips, flip chips with missing solder joints, and flip chips with open solder joints. They are recognized under the features selected by genetic algorithms rapidly and accurately, compared with those under other feature datasets, demonstrating that the approach using genetic algorithms is effective for defect inspection in flip chip packaging.