Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages

Solder bumps serve as electrical paths as well as structural support in a flip-chip package assembly. Owing to the differences of feature sizes and electric resistivities between a solder bump and its adjacent traces, current densities around the regions where traces connect the solder bump increase in a significant amount. This current crowding effect along with the induced Joule heating would accelerate fatigue failure due to electromigration. In this paper we apply the three-dimensional electrothermal coupling analysis to investigate current crowding and Joule heating in a flip-chip package assembly carrying different constant electric currents under different ambient temperatures. Experiments are conducted to calibrate temperature-dependent electric resistivities of solder alloy, Al trace, and Cu trace, and to verify the numerical model by comparing calculated and measured maximum temperatures on the die surface. Through the electrothermal coupling analysis, effects of current crowding and Joule heating induced by different solder bump structures are examined and compared.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Electromigration Behavior in Sn-37Pb and Sn-3.0Ag-0.5Cu Flip-Chip Solder Joints under High Current Density

The electromigration of conventional Sn-37Pb and Pb-free Sn-3.0Ag-0.5Cu (in wt.%) solder bumps was investigated with a high current density of 2.5 × 10⁴ A/cm² at 423 K using flip-chip specimens comprised of an upper Si chip and a lower bismaleimide triazine (BT) substrate. Electromigration failure of the Sn-37Pb and Sn-3.0Ag-0.5Cu solder bumps occurred with complete consumption of electroless Ni immersion Au (ENIG) underbump metallization (UBM) and void formation at the cathode side of the solder bump. Finite element analysis and computational simulations indicated high current crowding of electrons in the patterned Cu on the Si chip side, whereas the solder bumps and Cu line of the BT substrate had a relatively low density of flowing electrons. These findings were confirmed by the experimental results. The electromigration reliability of the Sn-3.0Ag-0.5Cu solder joint was superior to that of Sn-37Pb.     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Effect of Al-Trace Width on the Electromigration Failure Time of Flip-Chip Solder Joints

The effect of Al-trace width on electromigration (EM) in flip-chip solder joints was investigated experimentally. EM tests were performed on eutectic Sn-Ag solders with 40-μm- and 100-μm-wide Al traces. Under the same stressing conditions (0.5 A at 165°C), the failure time was 44.1 h for solder joints with 40-μm-wide traces and 250.1 h for solder joints with 100-μm-wide traces. The Al-trace width influenced both the current crowding and the Joule heating effects. Thus, both effects are responsible for the significant difference in failure time. Finite-element analysis was used to examine the current crowding effect in solder bumps with Al traces of the two different widths. The results showed that the current crowding effect was slightly higher in joints with 40-μm-wide traces. In addition, the temperature coefficient was used to measure the real temperatures in the solder bumps during EM. The results indicated that the width of the Al traces had a substantial influence on the Joule heating effect. The measured temperature in the solder bump was 218.2°C and 172.2°C for the bump with 40-μm- and 100-μm-wide Al traces, respectively. This difference in the Joule heating effect plays a crucial role in causing the difference in the failure time of solder joints with the two different widths.     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

Connection of VLSI chips to printed circuit board using stacked solder bumps

A new type of flip-chip interconnection technology usingstacked solder bumps is proposed, where the diameter of theupper solder bump is less than that of the lower ones. This isto reduce the capacitance between the stacked solder bumps and the ground plane and to prolong the lifetime ofthe solder joints.     

Temperature and current-density distributions in flip-chip solder joints with Cu traces

Three-dimensional simulation was performed to investigate the temperature and current density distribution in flip-chip solder joints with Cu traces during current stressing. It was found that the Cu traces can reduce the Joule heating effect significantly at high stressing currents. When the solder joints were stressed by 0.6 A, the average temperature increases in solder bumps with the Al traces was 26.7°C, and it was deceased to 18.7°C for the solder joint with the Cu traces. Hot spots exist in the solder near the entrance points of the Al or Cu traces. The temperature increases in the hot spot were 29.3°C and 20.6°C, for solder joints with the Al traces and Cu traces, respectively. As for current density distribution, the maximum current density inside the solder decreased slightly from 1.66×10⁵ A/cm² to 1.46×10⁵ A/cm² when the Al traces were replaced by the Cu traces. The solder joints with the Cu traces exhibited lower Joule heating and current crowding effects than those with the Al traces, which was mainly attributed to the lower electrical conductivity of the Cu traces. Therefore, the solder joints with the Cu traces are expected to have better electromigration resistance.     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

超声扫描显微镜检查在倒装器件检测中的应用

随着倒装器件在型号产品中使用越来越广泛,倒装器件在使用过程中也暴露出一些问题,如底充胶分层、焊点空洞以及裂纹等,这些缺陷均能导致倒装器件失效。总结了几种倒装器件超声扫描的缺陷,重点对底充胶以及焊点进行分析。同时,论述了倒装器件超声检测中内部界面缺陷的辨别以及原理。     

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives. An erratum to this article is available at .     

Electromigration study in SnAg3.8Cu0.7 solder joints on Ti/Cr-Cu/Cu under-bump metallization

This paper investigates the electromigration-induced failures of SnAg3.8Cu0.7 flip-chip solder joints. An under-bump metallization (UBM) of a Ti/Cr-Cu/Cu trilayer was deposited on the chip side, and a Cu/Ni(P)/Au pad was deposited on the BT board side. Electromigration damages were observed in the bumps under a current density of 2×10⁴ A/cm² and 1×10⁴ A/cm² at 100°C and 150°C. The failures were found to be at the cathode/chip side, and the current crowding effect played an important role in the failures. Copper atoms were found to move in the direction of the electron flow to form intermetallic compounds (IMCs) at the interface of solder and pad metallization as a result of current stressing.     

Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).     

Simulation and measurement of the flip chip solder bumps with a Cu-plated plastic core

With the aim to miniaturize and to reduce the cost, the increasing demand, regarding to advanced 3D-packages as well as high performance applications, accelerates the development of 3D-silicon integrated circuits. The trend to smaller and lighter electronics has highlighted many efforts towards size reduction and increased performance in electronic products. The radio frequency (RF) performances are limited by parasitic effects due to the resistor–inductor–capacitor (RLC) network, between the wire bond connections from the dies to the lead frame. The use of flip-chip bonding technology for very fine pitch packaging allows high integration and limits parasitic inductances. Electromigration (EM) and thermomigration (TM) may have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. A possibility to extend the reliability is the use of plastic ball in the solder bumps. Bumps containing a plastic solder balls have an excellent reliability. Using a plastic ball with a low Young modulus, the solder hardness is moderated and the stress on a ball is relaxed. Due to this, the stress does not concentrate on the solder joint which prolongs the lifetime. In this investigation, the thermal–electrical–mechanical coupling of electromigration on bumps containing a plastic solder is studied.     

凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

Relieving Hot-Spot Temperature and Current Crowding Effects During Electromigration in Solder Bumps by Using Cu Columns

Solder joints with Cu columns appear to be one of the best structures to resist electromigration. Three-dimensional thermoelectrical analysis was employed to simulate the current density and temperature distributions for eutectic SnPb solder bumps with 0.5, 5, 25, 50, and 100 μm Cu under bump metallization (UBM). It was found that the hot spots and current crowding effects in the solder were reduced significantly when the Cu thickness was over 50 μm, whereas the overall Joule heating effect remained almost unchanged. The mechanism by which the Cu column is effective in relieving the hot spot and current crowding effects is to keep the solder away from the heat source and crowding region. Simulated at a current of 0.6 A and 70°C, the estimated mean time to failure of the joints with a 50-μm-thick Cu column was 6.7 times longer than that of joints with a 0.5-μm-thick Cu UBM.