含存储器数字电路板的TPS开发研究

提出了含存储器数字电路板的两种测试矢量集(TPS)开发方案.对含少量存储器芯片的电路板采用结构化的测试方案,即将RAM等效成时序电路模型,利用时序电路ATPG软件进行测试生成.对以RAM为主的存储器板提出了一种功能测试方案,采取压缩地址空间的方法,对RAM阵列进行读写操作.实际应用证明,这两种方案较好地满足了实际应用中的需要.     

Highly Anisotropic Suspended Planar‐Array Chips with Multidimensional Sub‐Micrometric Biomolecular Patterns

Suspended planar‐array (SPA) chips embody millions of individual miniaturized arrays to work in extremely small volumes. Here, the basis of a robust methodology for the fabrication of SPA silicon chips with on‐demand physical and chemical anisotropies is demonstrated. Specifically, physical traits are defined during the fabrication process with special focus on the aspect ratio, branching, faceting, and size gradient of the final chips. Additionally, the chemical attributes augment the functionality of the chips with the inclusion of complete coverage or patterns of selected biomolecules on the surface of the chips with contact printing techniques, offering an extremely high versatility, not only with the choice of the pattern shape and distribution but also in the choice of biomolecular inks to pattern. This approach increases the miniaturization of printed arrays in 3D structures by two orders of magnitude compared to those previously demonstrated. Finally, functional micrometric and sub‐micrometric patterned features are demonstrated with an antibody binding assay with the recognition of the printed spots with labeled antibodies from solution. The selective addition of physical and chemical attributes on the suspended chips represents the basis for future biomedical assays performed within extremely small volumes.     

微反应槽PCR芯片阵列温度控制系统

设计了内部不含传感元件、加热元件的低成本微反应槽聚合酶链式反应(PCR)芯片,研制了宏观集中控制与微观分散控制有机结合的PCR芯片阵列温度控制系统。宏观集中控制装置以水为媒质通过特制换热器给芯片提供聚合酶链式反应所需的基本温度;在柔性印刷电路板上形成与芯片阵列对应的微型加热器阵列,针对各芯片进行分散的温度补偿。采用串级控制获得微加热器阵列与换热器之间的良好配合,实现各芯片准确、快速的温度控制。     

大面阵碲镉汞芯片的热应力分析与优化

随着红外焦平面探测器面阵规模的不断扩大,大面阵碲镉汞芯片的热应力进一步恶化,受温度冲击后更容易产生损伤,进而直接影响探测器的使用,甚至导致探测器失效。这已成为大面阵探测器生产工艺亟需解决的问题。借助仿真手段研究了大面阵碲镉汞芯片的低温损伤原因,并结合小面阵探测器进行了对比分析。结果表明,铟柱与碲镉汞接触边缘部位因应力集中明显而成为损伤的起源点。不同材料的选择以及结构尺寸的设计有助于降低大面阵碲镉汞芯片的热应力和提高其工作可靠性。     

The Retinomorphic Approach: Pixel-Parallel Adaptive Amplification, Filtering, and Quantization

I describe a vision system that uses neurobiologicalprinciples to perform all four major operations found in biologicalretinae: (1) continuous sensing for detection, (2) local automaticgain control for amplification, (3) spatiotemporal bandpass filteringfor preprocessing, and (4) adaptive sampling for quantization.All four operations are performed at the pixel level. The systemincludes a random-access time-division multiplexed communicationchannel that reads out asynchronous pulse trains from a 64×64 pixel array in the imager chip, and transmitsthem to corresponding locations on a second chip that has a 64×64 array of integrators. Both chips are fully functional.I compare and contrast the design principles of the retina withthe standard practice in imager design and analyze the circuitsused to amplify, filter, and quantize the visual signal, withemphasis on the performance trade-offs inherent in the circuittopologies used.     

Demonstration of low voltage field emission

The authors describe field emission from a thin-film field emitter array. The process used to fabricate the field emitters is based on the mold technique described by H.F. Gray and R.F. Greene (US patent 4,307,507). Each emitter chip consists of a 10×10 square array of field emitter tips and associated lead bonding pads. There is a 10-μm spacing between emitter tips. The bare chips were packaged by mounting to an alumina substrate, four to eight chips per substrate. The chips were tested in a demountable vacuum system equipped with a movable anode. The testing apparatus makes it possible to accurately measure currents as low as 100 nA at low duty. Fowler-Nordhein-like current-voltage characteristics were measured for most of the chips tested, indicating field emission. Substantial emission currents were observed at less than 20 V. The emitted current was collected almost entirely at the anode: the measured gate current was 1 to 5% of the emitted current     

Study of 90-nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

We report 90-nm MOSFET subthreshold hump characteristics obtained for the first time by using a newly developed MOSFET array test structure. The array contains small-scale device-under-test groups with a new poly-Si gate layout pattern, which eliminates the influence of gate leakage and off leakage currents observed on measured MOSFET parameter data such as Vth, Ion, and subthreshold slope. We confirmed that subthreshold humps occur at random in an array. The rate at which humps occur is expressed as a percentage with respect to the whole array (referred to as the hump occurrence rate); the rate depends on chips from a wafer. It is also confirmed that the influence of subthreshold humps on /spl sigma/(Vth) is not negligible, and we revealed that it is important to design RF/analog circuits with an appropriate current density to reduce their influence. By extracting hump variations using a MOSFET array, it is possible to accurately estimate and reduce the standby current in logic large-scale integration (LSI) chips.     

基于低温共烧陶瓷技术的Ku波段低噪声放大器

设计了一种基于低温共烧陶瓷(Low temperature co-fired ceramic)技术的Ku波段低噪声放大器。将低噪声放大器的MMIC芯片集成于LTCC基板中,利用三维全波电磁场软件设计和优化了LNA的无源模型,包括金丝、通孔阵列和多层地平面。金丝用来连接MMIC芯片和微带,通孔用来连接不同地平面。分析了两根平行金丝的π型等效模型并提取了该模型的参数,研究了通孔阵列的间距以得到良好的接地效果。为了得到LNA完整的仿真,将整个无源模型的电磁场数据导出到ADS软件中,并和MMIC芯片的S参数一起协同仿真,最终得到优化结果。测试结果表明该LNA在12~17GHz的频段内,具有40dB的增益,±1.215dB的带内平坦度,2.9dB的噪声系数。     

基于BioMEMS技术的样品预处理微流控芯片研制

研制了细胞分离芯片和DNA提取芯片两种样品预处理微流控芯片,介绍该两种芯片的原理、结构和样品预处理效果。基于微过滤原理设计的闸式细胞分离芯片,可实现老鼠外周血中白细胞与红细胞的分离。DNA提取芯片是基于固相萃取原理设计,研制成Si-玻璃和Si-PDMS-玻璃两种结构的DNA提取芯片。采用深刻蚀技术在硅片上刻蚀出20μm宽方柱阵列或直径为10μm的圆柱阵列,刻蚀深度为30～150μm,微柱阵列作为提取DNA的固相载体,成功提取PCR产物中的DNA。     

Wafer-scale integration-a fault-tolerant procedure

Considers a new approach to full-slice technology in relation to existing procedures for achieving this goal. Under external control a chain of good chips is created to form a long serial memory from an array of identical chips on a full slice. Bad chips are automatically bypassed without requiring any pre- or post-programming of the metallization and without any prior knowledge of the distribution of faulty chips on the wafer. Computer simulations of chain formation are described which demonstrate the feasibility of creating such serial memories at practicable dice-yield levels. The proposed logic design is summarized and its verification by TTL simulation is noted. The inherent fault and failure tolerance of the design are discussed and the potential problem areas of short-circuit chips, double-level metallization, spiral branching, thermal dissipation, and noise/pattern sensitivity are described together with suggested solutions.     

A Highly Reliable Memory Subsystem Design Employing SECDED, Column Sparing, and Paging

This paper develops a reliability model for a paged memory system wherein the pages of memory are physically distributed among several arrays of memory chips. Any of the available pages can be used to satisfy the required memory capacity. This paper also develops a reliability model for a page or block of memory words imbedded in an array. The model assumes that memory chips have failure modes that are catastrophic to a row, to a column, to the whole physical array, or to individual bits. Spare columns or data lines are used to enhance reliability. SECDED (Single Error Correction, Double Error Detection) provides the hard-fault detection mechanism and complete fault coverage for soft faults such as 1-bit upsets. A highly reliable memory system design is described that implements a paging scheme, uses a SECDED code for hard fault detection and isolation, and uses three levels of sparing to recover from failures. The significance of this paper is that it considers failure modes associated with interfacing a memory chip into an array of memory chips. These failure modes have an impact beyond the boundaries of an individual chip; they affect the entire physical array and must be considered in the reliability model. When this is done the reliability model permits trading off page size and array size with reliability.     

MUSIC算法在高速DSP上的并行实现

在 4片TI公司的高速DSP芯片 (TMS32 0C4 0 )上并行地实现了阵列测向中的MUSIC方法。在实现过程中 ,采取了一些有效的措施减少了计算量 ,指出了在均匀圆阵和均匀线阵的谱峰搜索中具有很大的计算冗余性 ,这些都有助于缩短信号处理时间。     

A reliability-driven placement procedure based on thermal-force model

This paper deals with placing chips on an MCM substrate in chip array style for minimizing the system failure rate. The placement procedure begins with constructing an initial placement based on cooling considerations. Then, a thermal-force model is presented to transform the reliability-driven placement problem to solve a set of simultaneous nonlinear equations to determine thermal-force-equilibrium locations of the chips. A modified Newton–Raphson method is used to solve this system of equations. Finally, a chip assignment procedure transforms the thermal-force-equilibrium placement into an array style placement for minimum thermal distortion. Two assignment methods are developed and compared each other. Experiments on three industrial MCMs designed by IBM show that the obtained placements have significant improvements to their original designs in system reliability. Additionally, a simulated annealing approach is presented for justifying the performance of the proposed method.     

Yield enhancement of bit level systolic array chips using fault tolerant techniques

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics we demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.     

Hybrid-integrated 4×4 optical gate matrix switch usingsilica-based optical waveguides and LD array chips

The fabrication and characteristics of a hybrid-integrated optical gate matrix switch were studied. The switch was composed of a silica-based single-mode guided-wave circuit and two InGaAsP gate array chips, each of which comprised eight laser diode optical gates. The gate array chips were assembled on the guided-wave circuit using a hybrid integration technique. The insertion loss of the fabricated 4×4 matrix switch was scattered among switching paths and ranged from 26 to 33 dB. The switch was applicable to a 400 Mb/s signal system with a bit error rate of 10^-9. The numerical analysis shows that the residual reflectivity at the LD gate and waveguide facets caused the loss scattering among the paths and that reduction of the residual reflectivity is essential for improving the switch characteristics     

Packaging for a 40-channel parallel optical interconnection modulewith an over-25-Gbit/s throughput

NTT is currently working on developing a high-throughput interconnection module that is both compact and cost effective. The technology being developed is called “parallel inter-board optical interconnection technology”, or “ParaBIT”. The ParaBIT module that has been developed is the first step; it is a front-end module with 40 channels, a throughput of over 25 Gbit/s, and a transmission distance of over 100 m along multimode fibers. One major feature of this module is the use of vertical-cavity surface-emitting laser (VCSEL) arrays as very cost-effective light sources. These arrays enable the same packaging structure to be used for both the transmitter and receiver. To achieve super-multichannel performance, high-density multiport bare-fiber (BF) connectors were developed for the module's optical interface. Unlike conventional optical connectors, these BF connectors do not need a ferrule or spring. This ensures physical contact with an excellent insertion loss (less than 0.1 dB per channel). A polymeric optical waveguide film with a 45° mirror for coupling to the VCSEL and photo-diode (PD) arrays by passive optical alignment was also developed. To facilitate coupling between the VCSEL/PD array chips and the waveguide, a packaging technique was developed to align and die bond the optical array chips on a substrate. This technique is called transferred multichip bonding (TMB); it can be used to mount optical array chips on a substrate with a positioning error of only several micrometers. These packaging techniques enabled ultra-parallel interconnections to be achieved in prototype ParaBIT modules     

微透镜阵列提高LED多芯片封装取光效率的仿真

提出在LED多芯片平面封装表面添加微透镜阵列,以提高取光效率。仿真分析了微透镜阵列的半径、间距和排列方式等对取光效率的影响。分析结果表明,通过在封装平面添加微透镜阵列,可以极大地提高取光效率,微透镜的填充因子是影响取光效率大小的关键因素,填充因子越大,则其取光效率越高;微透镜的排列方式对出射光强的分布也会产生影响。     

Finding the Next Computational Model: Experience with the UCSC Kestrel

Architects and industry have been searching for the next durable computational model, the next step beyond the standard CPU. Graphics co-processors, though ubiquitous and powerful, can only be effectively used on a limited range of stream-based applications. The UCSC Kestrel parallel processor is part of a continuum of parallel processing architectures, stretching from the application-specific through the application-specialized to the application-unspecific. Kestrel combines an ALU, multiplier, and local memory, with Systolic Shared Registers for seamless merging of communication and computation, and an innovative condition stack for rapid conditionals. The result has been a readily programmable and efficient co-processor for a wide range of applications, including biological sequence analysis, image processing, and irregular problems. Experience with Kestrel indicates that programmable systolic processing, and its natural combination with the Single Instruction-Multiple Data (SIMD) parallel architecture, is the most powerful, flexible, and power-efficient computational model available for a large group of applications. Unlike other approaches that try to displace or replace the standard serial processor, our model recognizes that the expansion in the application landscape and performance requirements simply imply that the most efficient solution is the combination of more than one type of processor. We propose a model in which the CPU and the GPU are complemented by “the third big chip,” a massively-parallel SIMD processor.     

高速大容量FLASH存储系统设计

介绍所设计的高速、大容量存储卡的组成机制和系统实现方案.采用固态存储芯片FLASH(闪存)为存储介质,FPGA(现场可编程门阵列)为存储阵列的控制核心,针对外部高速数据的输入,引入了多级流水和冗余校验技术,并自动屏蔽了FLASH的坏块.成功实现了用高密 度、相对低速的FLASH存储器对高速实时数据的可靠存储.另外,通过USB和CPCI接口,可以同主机进行良好的数据通信.     

一种C波段数字阵列模块设计与研究

介绍了一种C波段数字阵列模块的设计,该模块可应用于数字阵列雷达中,该模块包含独立可控的多个通道,易于实现收发数字波束形成,阵列模块中电路共用部分均采用集中供给,将混频器、滤波器等器件采用收发共用,使得阵列模块的集成度大幅提高。