An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n/sup +/ diodes

Snapbacks in sustain characteristics of lateral double-diffused MOSFETs (LDMOSFETs) are caused by positive feedbacks between the turn-on of the bipolar junction transistors (BJTs) and the avalanche breakdown of the drain n-n/sup +/ diodes . Although the n-n/sup +/ diodes are thus one of the most basic parasitic devices, which play a leading role in the snapback characteristics, neither a textbook nor a paper has ever described their breakdown characteristics in depth so as to realize a simple no-snapback LDMOSFET. This paper analyzes the snapback characteristics of n-n/sup +/ diodes and their mechanisms in detail. The no-snapback theory derived from this study is applied to an advanced no-snapback LDMOSFET with a simple structure, as an improved version of the conventional no-snapback LDMOSFET , which endures the electrostatic discharge (ESD) criterion for automotive applications: 15 kV, 150 pF, and 150 /spl Omega/.     

A reverse-voltage protection circuit for MOSFET power switches

When MOSFET is used as a power switch, it is essential to prevent reverse current flow through the parasitic body diodes under reverse voltage condition. A new built-in reverse voltage protection circuit for MOSFETs has been developed. In this design, an area-efficient circuit is used to automatically select the proper well bias voltage to prevent reverse current under the reverse-voltage condition. This built-in reverse protection circuit has been successfully implemented in a high-side power switch application using a 0.6-μm CMOS process. The die area of the protection circuit is only 2.63% of that of a MOSFET. The latch-up immunity is greater than +12 V and -10 V in voltage triggering mode, and greater than ±500 mA in current triggering mode. The protection circuit is not in series with the MOSFET switch, so that the full output swing and high power efficiency are achieved     

Study on the device characteristics of a quasi-SOI power MOSFETfabricated by reversed silicon wafer direct bonding

The device characteristics of a quasi-SOI power MOSFET were investigated to obtain its optimum device structure. The oxide at the original bottom surface of the bulk power MOSFET of the quasi-SOI power MOSFET formed by reversed silicon wafer direct bonding acts as the buried oxide of the conventional SOI power MOSFET. The short channel effect of the quasi-SOI power MOSFET was larger than that in the conventional SOI power MOSFET. It was suppressed by increasing the width of the oxide in the body region, and the parasitic bipolar effect was suppressed by decreasing it. We also propose a new device structure which can suppress the short channel effect and parasitic bipolar effect of a quasi-SOI power MOSFET based on the results of these experiments     

Surface accumulated lateral npn BJT's characteristics in SOINMOSFETs

Lateral npn bipolar junction transistors (BJTs) in SOI MOSFET structures are investigated under various gate voltages. Negative resistance caused by base resistance modulation is observed. The surface-accumulated BJT mode is superior to the MOSFET mode in transconductance-to-current ratio and output resistance. Scaling properties are also discussed together with the need for a P⁺ polysilicon gate     

Devices and circuits for bipolar (V)LSI

It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit. General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor fT, and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes. Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design. Logic circuits (such as I²L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed.     

A zero-voltage-switched three-phase interleaved buck converter

This paper proposes a three-phase interleaved buck converter which is composed of three identical paralleled buck converters. The proposed solution has three shunt inductors connected between each other of three basic buck conversion units. With the help of the shunt inductors, the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Furthermore, the decreasing rate of the current through the free-wheeling diodes is limited, and therefore, their reverse-recovery losses can be minimised. The active power switches are controlled by interleaved pulse-width modulation signals to reduce the input and output current ripples. Therefore, the filtering capacitances on the input and output sides can be reduced. The power efficiency is measured to be as high as 98% in experiment with a prototype circuit.     

Fabrication and characterization of heterojunction diodes withHVPE-grown GaN on 4H-SiC

GaN/SiC heterojunctions can improve the performance considerably for BJTs and FETs. In this work, heterojunction diodes have been manufactured and characterized. The fabricated diodes have a GaN n-type cathode region on top of a 4H-SiC p-type epi layer. The GaN layer was grown with HVPE directly on off-axis SIC without a buffer layer. Mesa structures were formed and a Ti metallization was used as cathode contact to GaN, and the anode contact was deposited on the backside using sputtered Al. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed on the diode structures. The ideality factor of the measured diodes was 1.1 and was constant with temperature. A built in potential of 2.06 V was extracted from I-V measurements and agrees well with the built in potential from C-V measurements. The conduction band offset was extracted to 1.1 eV and the heterojunction was of type II. The turn on voltage for the diodes is about 1 V lower than expected and a suggested mechanism for this effect is discussed     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

寄生电感对碳化硅MOSFET开关特性的影响

相比于传统的Si IGBT功率器件而言,碳化硅MOSFET可达到更高的开关频率、更高的工作温度以及更低的功率损耗.然而,快速的暂态过程使开关性能对回路的寄生参数更加敏感.因此,为了评估寄生电感对碳化硅MOSFET开关性能的影响,基于回路电感的概念,将栅极回路寄生电感、功率回路寄生电感以及共源极寄生电感等效成3个集总电感,并且从关断过电压、开通过电流及开关损耗等3个方面,对这3个电感对SiC MOSFET开关性能的影响进行了系统的对比研究.研究表明:共源极寄生电感对开关的影响最大,功率回路寄生电感次之,而栅极回路寄生电感影响最小.最后,基于实验分析结果,为高速开关电路的布局提出了一些值得借鉴的意见.     

Conduction power loss in MOSFET synchronous rectifier withparallel-connected Schottky barrier diode

The conduction power loss in an MOSFET synchronous rectifier with a parallel-connected Schottky barrier diode (SBD) was investigated. It was found that the parasitic inductance between the MOSFET and SBD has a large effect on the conduction power loss. This parasitic inductance creates a current that is shared by the two devices for a certain period and increases the conduction power loss. If conventional devices are used for under 1 MHz switching, the advantage of the low on-resistance MOSFET will almost be lost. To reduce the conduction loss for 10 MHz switching, the parasitic inductance must be a subnanohenley     

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25-μm base width have been successfully fabricated in a p-well 0.25-μm bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported     

基于MOSFET漏电流温度特性的室温红外探测器

基于MOSFET的漏电流温度特性，提出了一种可与CMOS工艺兼容的新型室温红外探测器。它采用在SOI衬底上实现的MOSFET作为探测红外灵敏元，在MOSFET的钝化层上制作可提高红外吸收率的光学谐振腔，并利用硅微机械加工技术将SOI的隐埋氧化层悬空，形成热绝缘微桥结构。MOSFET在担当探测红外辐射灵敏元的同时，又作为放大处理电路的一部分，简化了电路。分析表明，探测器的探测率可高达10^9-10^10cmHz^1/2W^-1.     

Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics

We proposed a new non-planar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts’ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress from the underlaying SiGe 3D islands. We show that more than 50% higher mobilities of electrons can be obtained as indicated by 3D simulations performed throughout the entire fabrication process. Then, fully-depleted SOI MOSFET and d-Dot MOSFET are compared in term of short channel effects, parasitic capacitance effects and self-heating effects.     

Bridge-arm current reduction in DC-AC inverter

When building single-phase inverter with power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), switching action may cause poor reverse recovery characteristic due to body parasitic diode of MOSFET, which can produce peak current in the circuit loop and the high transient voltage and current (dv/dt, di/dt) during the turning-on period. In this article, a novel method to reduce the bridge arm current spike in DC-AC inverter is proposed. The presented method uses the improved and simplified coupled inductor which is connected between the upper and lower power devices. The parasitic capacitors of MOSFET are charged and discharged by the coupled inductor and the energy is released in the new loop; therefore, the bridge peak current is diminished. The time-domain model of transient-state analyses is given in detail. The current spike of the main switch is clamped efficiently. By increasing switching frequency, the volume of the magnetic core can be further reduced which is resulted from reduction in the reverse recovery current in parasitic diode. Because of the suppression of the spike current via the device, the switch-on loss of the power loss is reduced, and low on-state resistor of the power device can be adopted to suppress the conduction loss. The proposed approaches are validated with experimental results.     

Holding voltage investigation of advanced SCR-based protection structures for CMOS technology

A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D-device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 °C − 125 °C). Using device simulation results, the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed.     

Simulation of thermal effects in integrated circuits with SPICE - a behavioural model approach

This paper reviews an approach to the simulation of thermal effects in integrated circuits with SPICE by using an analog behavioural modelling concept. Macro models for BJTs, diodes and resistors are presented, which consider the influence of self-heating, interaction thermals, as well as the nonlinear thermal conductivity of silicon on the circuit's behaviour. Such simulations give a first insight into the thermal sensitivity of the circuitry, even in a very early design phase.     

Nondestructive RBSOA characterization of IGBTs and MCTs

Nondestructive evaluation of IGBTs and MCTs are reported and their corresponding reverse bias safe operating areas (RBSOAs) established. It was observed that compared to BJTs, IGBTs and MCTs exhibit very different turn-off breakdown characteristics. Avalanche breakdown of the parasitic transistor accounts for the loss of dynamic voltage blocking capability of both IGBTs and MCTs     

A new type of transistor: CBT

A transistor called the channel-base transistor (CBT), which is constructed by making channels through the base of the conventional bipolar junction transistors (BJTs), is proposed. In principle, a CBT can be treated as a combination of a BJT and a normally-off junction-type field-effect transistor (E-JFET). Silicon planer CBTs have been fabricated with BJTs on the same wafer for comparison. The electrical characteristics of CBTs are similar to those of a conventional BJTs, but the variations of current gain with temperature and emitter current in CBTs are much less than those in the BJTs. In addition, the magnitude of current gain of CBTs is higher than that of comparable BJTs. Transistor-transistor-logic (TTL) NAND-gate ICs implemented with CBTs have been fabricated. The temperature variations of parameters in CBT ICs are less than those in BJT ICs. Experiments have shown that silicon CBT discrete devices and ICs can be used over a wide range of temperatures from -60°C to 200°C. Experimental and theoretical analysis results for CBTs are presented     

Physical phenomena affecting performance and reliability of 4H-SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300 A/cm². However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H-SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N-P-N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.     

基于平面肖特基二极管的W波段检波器

肖特基二极管技术为常温下毫米波信号的检测提供了有效的解决方案。它具有极低的寄生电容和级联电阻,可用于该频段的倍频器、混频器和检波器当中。相比于Galey Cell和热辐射测定器(Bolometer),基于肖特基二极管的直接检波技术具有低噪声、高反应率和常温使用的特点。本文介绍了一种基于波导结构的零偏置肖特基二极管检波器,采用E面探针传输波导基模电磁波,通过阻抗匹配实现微带线到二极管的耦合。测试结果表明,在-30 dBm输入功率下：电压反应率的峰值可达8 900 V/W;在75 GHz~105 GHz的频率范围内,电压反应率在1 000 V/W以上。