.NET组件和COM组件的应用集合研究

组件对象模型（COM）为代码的重用性提供了一种模块化和面向对象的技术标准。.NET组件是微软公司在 .NET平台上发布的新一代组件模型。文中介绍了 .NET组件和COM组件的互操作性以及 .NET组件的原理和体系结构，并以手机接口平台为技术背景，讨论了如何在两个不同平台上对COM和 .NET组件进行融合，针对此类应用提出了系统设计、体系结构和功能构成等应用方案，较详细地讨论了在非 .NET平台上调用.NET组件。     

实施系统封装方案以提高系统整体功能和性能

系统集成是实现电子产品高性能,小型化和低成本目标的重要手段。与同芯片上的系统集成(SoC)相比,封装层次上的系统集成(SiP)的开发具有成本低、周期短和灵活性高等优势。本文以典型的无线电子系统为例,提出了有效的系统分割设计方法,介绍了一些用于子系统模块封装的方法,并强调了系统公司与封装、基板及其它主被动元件供应商之间协调合作对成功的模块式电子系统开发的重要性。     

Cutting the high cost of testing

A modeling approach to the overly long testing of analog and mixed-signal devices that saves substantially on time and cost is described. The discussion focuses on the particular case of a 13 bit analog-to-digital converter (ADC). The problems that arise in testing ADCs are identified, showing that the success of the test method depends critically on the quality of the model. Two types of models are examined, physical-sensitivity-based models and empirical-learning-based models, and it is noted that the latter are especially attractive for performance-testing applications like the ADC example. An 18-parameter model of the 13 bit ADC was developed using a combination of physical and empirical modeling techniques and was highly successful. With an array process to speed up the computations, the computational overhead can be kept below 1 s per device, so the test time, which is reduced by a factor of 128, becomes negligible     

A reliability and cost analysis of an automatic prototype generatortest paradigm

A cost and reliability model which uses an automatic prototype generator (APG) is presented. According to this model, testers can introduce rapidly prototyped automatically generated codes into the testing phase. The model is called the APG test paradigm (APGTP). Two cases are considered: without a budget constraint, and with both a budget constraint and an objective to maximize the outgoing product reliability. Increased reliability can be attained by applying a five-step procedure. It is shown that the capital requirement for an APG exceeds the available installation cost, then installation of the APG should not be considered unless its reliability per dollar invested exceeds that of the traditional model. To demonstrate the procedures, the costs and reliabilities of the two approaches are compared for certain specified parameter values. The use of APGTP generally produces code of better reliability for the same cost as in traditional testing proposed by D.B. Brown and S. Maghsoodloo (1989)     

Optimal release time for software systems considering cost, testing-effort, and test efficiency

In this paper, we study the impact of software testing effort & efficiency on the modeling of software reliability, including the cost for optimal release time. This paper presents two important issues in software reliability modeling & software reliability economics: testing effort, and efficiency. First, we propose a generalized logistic testing-effort function that enjoys the advantage of relating work profile more directly to the natural flow of software development, and can be used to describe the possible testing-effort patterns. Furthermore, we incorporate the generalized logistic testing-effort function into software reliability modeling, and evaluate its fault-prediction capability through several numerical experiments based on real data. Secondly, we address the effects of new testing techniques or tools for increasing the efficiency of software testing. Based on the proposed software reliability model, we present a software cost model to reflect the effectiveness of introducing new technologies. Numerical examples & related data analyzes are presented in detail. From the experimental results, we obtain a software economic policy which provides a comprehensive analysis of software based on cost & test efficiency. Moreover, the policy can also help project managers determine when to stop testing for market release at the right time.     

Trade-off analysis on cost and manufacturing technology of an electronic product: Case study

A trade-off analysis on the cost and system packaging metrics of an electronic product aimed at the commercial/retail industry has been carried out. By comparing the system cost and packaging metrics with those of comparable consumer products, we have determined that there is opportunity for significant cost, size, and weight reduction of the overall electronics packaging system. These include the use of fine pitch IC packages, smaller discrete components, denser PCB wiring technology, double sided IC package surface mount, surface mount connectors, and improved plastics for the product housing. The analysis concluded that PCB area reduction of 40%, using a single PCB instead of three boards, reduction in board cost of over 50% and product weight reduction of over 28% are possible using available technologies.     

An approach to deal with packaging in power electronics

Current packaging technology in power electronics is based on assembling pre-manufactured discrete components. Each component consists of a number of parts, manufactured in a variety of manufacturing processes. This has resulted in a diversity of construction parts and mutually incompatible manufacturing processes in a typical power electronic converter and has brought power electronics to the edge where it becomes extremely difficult to reduce the cost and size of power electronic converters. This also makes integration of power electronic converters difficult. In this paper, we present a way to improve the physical construction of power electronic converters by increasing level of integration and using multifunctional construction parts. integration and packaging are two important aspects of physical construction of power electronic converters. Both of them and their mutual relationship are discussed in the paper. Three quantities intended to evaluate integration level and volumetric utilization namely functional elements integration level, K/sub I/; packaging elements integration level K/sub P/; and volumetric packaging efficiency /spl eta//sub v/ are introduced. Based on these values, a number of techniques to increase the integration level are presented. A design process in the form of a flowchart intended to implement these techniques in concrete design cases is presented.     

Efficient object-oriented integration and regression testing

This paper presents a model, a strategy and a methodology for planning integration and regression testing from an object-oriented model. It shows how to produce a model of structural system test dependencies which evolves with the refinement process of the object-oriented design. The model (test dependency graph) serves as a basis for ordering classes and methods to be tested for regression and integration purposes (minimization of test stubs). The mapping from unified modeling language to the defined model is detailed as well as the test methodology. While the complexity of optimal stub minimization is exponential with the size of the model, an algorithm is given that: computes a strategy for integration testing with a quadratic complexity in the worst case; and provides an efficient testing order for minimizing the number of stubs. Various integration strategies are compared with the optimized algorithm (a real-world case study illustrates this comparison). The results of the experiment seem to give nearly optimal stubs with a low cost despite the exponential complexity of getting optimal stubs. As being a part of a design-for-testability approach, the presented methodology also leads to the early repartition of testing resources during system integration for reducing integration duration     

Optimal design of life testing for ULSI circuit manufacturing

The life testing of ultra large scale integration (ULSI) circuits is perhaps the most complex manufacturing process found today. This complexity is, in part, the result of product diversity, uncertainty, and changing technologies, and has caused the cost of testing for ULSI circuits to grow exponentially. The author develops a testing cost model and determines the optimum sample size on test which minimizes the expected total system cost assuming that the cost of waiting per unit time and the cost of placing an ULSI circuit on test are given. Numerical examples are also provided to illustrate the methods     

Testing Multilayer Flexible Wireless Multisensor Platforms

Smart wireless sensor systems that incorporate multiple sensors often cannot be implemented on a single chip. Advanced integration and assembly allows for a more complex conjugation and configuration of multiple system modules implemented under different technologies together in a small tiny package. In tiny sensor systems such as these, three common challenges seen across most platforms are: the difficult test access due to non-standard assembly and packaging, the testing of multiple heterogeneous sensor species, and the strict dimensional requirements limiting availability of any built-in hardware for testing. We discuss the method of testing by modules for testing a multilayer mechanically flexible wireless multisensor platform. A hierarchical test flow is presented for verifying the functionalities and assessing the performance of the various modules of the system. We also present an example of a design for testing feature, a built-in test point access bus that improves reliability for test point access, reduces the cost of testing and overall system bill-of-material, as well, increases test channel bandwidth allowing for full access to all critical subsystem nodes. Lastly, we provide examples of subsystem performance assessment and verification testing of selected sensor species on the multisensor platform as well as the system power consumption versus transmission range, to illustrate the usefulness of the test concepts, flow, and features introduced.     

极大规模集成电路测试技术发展

集成电路作为新一代信息战略产业的基础,工艺、封装、应用的发展对测试提出了诸多挑战,同时测试作为集成电路产业链的一环,与设计、制造、封装等环节紧密相联。阐述了集成电路设计中高速、高集成度及测试成本对测试的挑战以及相应的测试解决方案,同时对测试与设计、封装、应用等产业链环节联接的典型技术如测试仿真到测试向量转换、inkless map、测试自动化数据等进行了描述。     

电子封装技术发展现状及趋势

现今集成电路晶圆的特征线宽进入微纳电子时代,而电子产品和电子系统的微小型化依赖先进电子封装技术的进步,封装技术已成为半导体行业关注的焦点之一。主要介绍了近年来国内外出现的有市场价值的封装技术,详细描述了一些典型封装的基本结构和组装工艺,并指出了其发展现状及趋势。各种封装方法近年来层出不穷,实现了更高层次的封装集成,因而封装具有更高的密度、更强的功能、更优的性能、更小的体积、更低的功耗、更快的速度、更小的延迟、成本不断降低等优势,其技术研究和生产工艺不可忽视,在今后的一段时间内将拥有巨大的市场潜力与发展空间,推动半导体行业进入后摩尔时代。     

High reliability, high density, low cost packaging systems formatrix systems for matrix BGA and CSP by vacuum printing encapsulationsystems (VPES)

Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology     

3D集成的发展现状与趋势

三维集成技术的发展是技术与理念的革新过程,本文根据集成封装技术的的发展历程,提出三维集成的发展特点,阐述理念的突破如何引导技术发展,以此为主线,可以更有逻辑性的了解三维集成的发展历史与趋势.封装从器件级向系统级的发展促使了多种系统级封装概念的出现;垂直堆叠方式推动互连长度不断降低;与晶圆级封装的结合可以大幅度降低成本;从同质向异质的转变则集成了多种学科、材料与技术,是实现复杂的系统的基础.     

Four-key-parts interworking model of heteromerous distributed component systems

The distributed component technology is increasingly widely used in the development and deployment of distributed systems. How to ensure interworking of these systems appears to be very important. On the basis of the in-depth study on distributed component systems, this article puts forward a four-key-parts interworking model and the corresponding static and dynamic translation mechanism for the integration of distributed component systems. Then, as a example, the interworking between common object request broker architecture (CORBA) component model (CCM) and enterprise Java bean (EJB) is discussed in detail. Thus, this paper offers an important idea for making various distributed component systems interworking and integration.     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of “big-D/small-A” mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal “big-D/small-A” SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.      

ROF技术在网络融合中的应用

光纤承载射频(ROF,Radio over Fiber)技术是一种先进的通信技术,它能有效的将光和微波技术结合在一起,具有大容量、低成本、易安装等优点。在移动通信中,最基本的要求是得到更丰富的传输带宽、无缝的覆盖范围和低功耗的传输效能。如果将ROF技术与现有网络技术融合起来,可以达到共享昂贵器件、集中控制、降低成本、动态分配网络容量的目的,也可以使移动通信的成本更低,集成化更高。主要介绍ROF技术的特点、ROF的关键技术、着重介绍ROF技术在网络融合中的重要应用。     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。