Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications     

Design and Implementation of Viterbi Decoder with FPGAs

In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. Viterbi decoder, constraint length seven, was designed and simulated with VHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.     

Guest Editors' Introduction

In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. Viterbi decoder, constraint length seven, was designed and simulated with VHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.

     

层次式布线资源FPGA连线开关的设计

提出了一种层次式布线资源FPGA连线开关的设计方法,采用迷宫算法,对连线开关的结构进行了分析.针对连线连接盒CB(connection box),提出了较为节省芯片面积的半连通结构;针对连线开关盒SB(switch box),在给出连通度fs概念后,提出了使SB连通能力达到最大值的设计方法,并通过数学推导予以证明.应用这种设计方法,设计了一种fs＝3的SB;成功地实现了采用这种结构的SB和半连通CB作为连线开关的FPGA芯片FDP-100K.该芯片在电路布通率和芯片面积方面取得了较好的平衡结果.     

Automatic synthesis of FPGA channel architecture for routabilityand performance

This paper considers automatic synthesis of segmented channel architecture of row-based FPGA's so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A channel architecture synthesis algorithm based on simulated annealing has been developed which enhances channel routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance. Excellent results have been obtained for a set of benchmark examples and industrial designs     

Routability improvement using dynamic interconnect architecture

We present a dynamic architecture for field programmable gate array (FPGA)-based computing systems with the introduction of dynamic field-programmable interconnection devices. The central principle of this new architecture is based on the concept of time-sharing, which we use to efficiently exploit the potential communication bandwidth of interconnection resources. This new architecture not only releases FPGA pin limitation to some degree, but also greatly increases the routability of interconnection networks, resulting in higher overall performance of FPGA-based systems     

Flexibility of interconnection structures for field-programmablegate arrays

The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility     

The Transmogrifier-2: a 1 million gate rapid-prototyping system

This paper describes the Transmogrifier-2 (TM-2), a second-generation multifield programmable gate array (FPGA) rapid-prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGA's, four I-Cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a nonuniform partial crossbar, that provides a constant delay between any two FPGA's in the system. The TM-2 architecture is modular and scalable, meaning that systems of various sizes can be constructed from copies of the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with edge resolution of 10 ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications     

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.     

PITIA: an FPGA for throughput-intensive applications

In this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new architecture, which targets datapath circuits, uses the concepts of wave steering and pipelined interconnects. We discuss the FPGA architecture and show results for performance, power consumption, clock network performance, and routability. Results for some commonly used datapath designs are encouraging with throughputs in the neighborhood of 625MHz in 0.25-/spl mu/m 2.5-V CMOS technology. Results for random benchmark circuits are also shown. We characterize designs according to their Rent's exponents and argue that designs with predominantly local interconnects are the best fit in PITIA. We also show that as technology scales down toward deep submicron, PITIA shows an increasing throughput performance.     

Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing

Multi-FPGA Boards (MFBs) have been in use for more than a decade for implementing systems requiring high performance and for emulation/prototyping of multimillion gate chips. It is important to develop an MFB architecture which can be used for emulation or prototyping of a large number of circuits. A key feature of an MFB is its routing architecture defined by its inter-Field-Programmable Gate Array (FPGA) connections. There are two types of inter-FPGA connections, namely–fixed connections (FCs) connecting a pair of FPGAs through dedicated wires and programmable connections (PCs) which connect a pair of FPGAs through a programmable switch. An architecture which has a mix of both these type of connections is called a hybrid routing architecture. It has been shown in the literature [7] that a hybrid MFB architecture is more efficient for emulation than an architecture with only one type of connections. The cost of an MFB and delay of the emulated circuit on it depends on the number of PCs used for emulation. An objective of a designer of an MFB for circuit emulation is to minimize the required number of PCs. In this paper, we describe algorithms to evaluate the requirement of PCs for many hybrid routing architectures.The requirement of PCs can be reduced if some programmable connections are replaced by a connection using only FCs by routing through FPGAs. Such a routing is called multi-hop routing. We present an optimal and a heuristic algorithm for estimation of PCs when limited number of hops through FPGAs are permitted. The unique feature of our evaluation scheme is that it is generic and treat routing architecture as a parameter. We have used benchmark circuits as well as synthetic cloned circuits for testing our algorithms. Our heuristic algorithm is very fast and gives optimal results most of the time. Our algorithms can be used for actual routing during circuit emulation.     

Architecture of field-programmable gate arrays

A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed     

SAT based solutions for detailed routing of island style FPGA architectures

Detailed routing solutions for island style FPGA architectures using Boolean satisfiability (SAT) based formulations have been proposed in this paper. Due to decreasing size of ICs and hence, the increasing complexity of the routing resource constraints, routing has been a big challenge in electronic design automation field. Our proposed techniques work on multi-pin net routing where all nets are considered for routing in their intact form whereas, most of the existing routing solutions decompose multi-pin nets into two-pin nets for detailed routing to ease the problem. However this approach, apart from increasing the number of nets in the circuits, may also introduce pin doglegging which, when not permitted by the architecture of FPGA, would require extra constraints to eliminate. Many detailed routers adopt sequential detailed routing approaches which are vulnerable to the net ordering problem which may cause a routable circuit to be erroneously classified as unroutable. Our proposed techniques avoid these pitfalls by keeping the multi-pin nets intact and solve all nets simultaneously using SAT. The SAT-based multi-pin net dogleg-free formulations presented here achieve significant improvement over existing SAT-based solutions with respect to the number of variables and clauses used, thereby achieving greater scalability and also display comparable and sometimes better routability results on benchmark circuits when compared with other detailed routing solutions. Detailed routing is also significantly affected by the architecture of the switching blocks. This paper proposes SAT-based formulation for three different switch box architectures i.e. Subset, Wilton, and Universal switches. Our experiments clearly demonstrate how routing solutions for a circuit can differ significantly for different types of switch boxes.     

FPGA routing and routability estimation via Boolean satisfiability

Guaranteeing or even estimating the routability of a portion of a placed field programmable gate array (FPGA) remains difficult or impossible in most practical applications. In this paper, we develop a novel formulation of both routing and routability estimation that relies on a rendering of the routing constraints as a single large Boolean equation. Any satisfying assignment to this equation specifies a complete detailed routing. By representing the equation as a binary decision diagram (BDD), we represent all possible routes for all nets simultaneously. Routability estimation is transformed to Boolean satisfiability, which is trivial for BDD's. We use the technique in the context of a perfect routability estimator for a global router. Experimental results from a standard FPGA benchmark suite suggest the technique is feasible for realistic circuits, but refinements are needed for very large designs     

Reliability and routability consideration for MCM placement

This paper presents a methodology based on the fuzzy logic approach for the placement of the power dissipating chips on the multichip module substrate. Our methodology considers both thermal distribution and routing length constraints during multichip module placement. In this paper, the main design issue is the coupled placement for reliability and routability. The objective of the coupled placement is to enhance the system performance and reliability by obtaining an optimal cost during multichip module placement. For reliability considerations, the design methodology is addressed on the placement of the power dissipating chips to achieve uniform thermal distribution. The thermal placement analysis is based on the modified fuzzy force-directed placement method. Placement for routability is based on minimizing the total wire length estimated by semi-perimeter method. The placement trade-off between routability and reliability is illustrated by varying a weighting factor. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated with the finite element method.     

基于FPGA的ACELP声码器的设计与实现

根据ACELP语音编码算法的原理,设计出一种新的基于FPGA实现ACELP语音编码算法的声码器系统.对比传统的DSP实现方法,该声码器系统可以保证良好的语音质量和较高的实时性,并且价格低廉,功耗小.     

Routability estimation of FPGA-based fault injection

In past years various approaches to hardware-based fault injection using FPGA-based systems have been presented. Owing to the generation of additional faulty functions the mapping and a routable placement of the circuit into the FPGA are difficult to achieve. A technique is presented for estimating the routability, which guarantees the routability of the faulty circuit in the FPGA.     

A Fault Tolerant Technique for FPGAs

In this paper we present a fault tolerant (FT) technique for field programmable gate arrays (FPGAs) that is based on incrementally reconfiguring circuits and applications that have been previously placed and routed. Our technique targets both logic faults and interconnect faults, and our algorithms can be applied to either static or run-time reconfigurable FPGAs. The algorithm for reconfiguring designs in the presence of logic faults uses a matching technique. The matching technique requires no preplaced, spare logic resources and is capable of handling groups of faults. Experimental results indicate there is little or no impact on circuit performance for low numbers of reconfigured logic blocks. For interconnect faults, we present a rip-up and reroute strategy. Our strategy is based on reading back the FPGA configuration memory, so no netlist is required for rerouting around faulty resources. Experimental results indicate high incremental routability for low numbers of interconnect faults. We also lay the foundation for applying our approach to yield enhancement.     

智能摄像系统视频采集模块的嵌入式结构

介绍的是实时视频采集模块的嵌入式结构,来实现智能的实时监控。嵌入式结构用赛灵思ML-507平台来进行开发。平台Virtex -5FXT FPGA设备中的FPGA结构中内嵌PowerPC440处理器,旋转变焦（PTZ）摄像机和VGA监视器与该平台连接。接口使用机载VGA输入视频编解码器和DVI发射器芯片。芯片的控制寄存器配置使用嵌入式PowerPC440处理器。应用软件用C语言编写。完成了视频的采集、传输、分辨率为640*480的显示。连接、处理能力高,FPGA消耗资源占18%,剩下的FPGA资源足够实现视频处理的应用。     

基于FPGA的开关盒互连容错算法的研究

FPGA主要由两个基本部分组成,一是可配置逻辑部件,另一部分就是互联网络,负责对可配置逻辑块间的通信。FPGA内部大约80%的晶体管都是作为可编程开关和缓冲器来完成可编程路由网络工作的。文中主要对出现错误的开关盒阵列中可执行的路径数量进行评估,并且使用算法找到合适的路径,避开错误。