High-resolution transmission electron microscopy calibration ofcritical dimension (CD) reference materials

The National Institute of Standards and Technology and Sandia National Laboratories have developed a procedure for producing and calibrating critical dimension (CD), or linewidth, reference materials. These reference materials will be used to calibrate metrology instruments used in semiconductor manufacturing. The reference features, with widths down to 100 nm, are produced in monocrystalline silicon with all feature edges aligned to specific crystal planes. A two-part calibration of these linewidths is used: the primary calibration, with accuracy to within a few lattice plane thicknesses, is accomplished by counting the lattice planes across the sample as-imaged through use of high-resolution transmission electron microscopy. The secondary calibration is the high-precision electrical CD technique. In this paper, we describe the calibration procedure for these reference materials and estimate the related uncertainties     

Extraction of sheet resistance from four-terminal sheet resistorsreplicated in monocrystalline films with nonplanar geometries

This paper describes limitations of conventional methods of extracting sheet resistance from four-terminal sheet resistors incorporated into electrical linewidth test structures that are patterned in (110) monocrystalline silicon-on-insulator (SOI) films. Nonplanar sections of these structures render the extraction of sheet resistance by conventional techniques subject to systematic errors. The errors are addressed here by algorithms incorporating the results of finite-element current flow analysis. The intended end application is to facilitate the use of the uniquely high repeatability and low cost of electrical critical dimension (CD) metrology as a secondary reference in a traceability path for CD-reference artifacts     

Electrical linewidth test structures patterned in (100)silicon-on-insulator for use as CD standards

Electrical test structures known as cross-bridge resistors have been patterned in (100) epitaxial silicon material that was grown on Bonded and Etched-back Silicon-On-Insulator (BESOI) substrates. The critical dimensions (CDs) of a selection of their reference segments have been measured electrically, by scanning-electron microscopy (SEM), and by lattice-plane counting. The lattice-plane counting is performed on phase-contrast images of the cross sections of the reference segments that are produced by high-resolution transmission-electron microscopy (HRTEM). The reference-segment features were aligned with (110) directions in the BESOI surface material. They were defined by a silicon micromachining process that resulted in their sidewalls being nearly atomically planar and smooth and inclined at 54.737° to the surface (100) plane of the substrate. SEM, HRTEM, and electrical CD (ECD) linewidth measurements have been made on features of various drawn dimensions on the same substrate to investigate the feasibility of a CD traceability path that combines the low cost, robustness, and repeatability of ECD metrology and the absolute measurement of the HRTEM lattice-plane counting technique. Other novel aspects of the (100) silicon-on-insulator (SOI) implementation that are reported here are the ECD test-structure architecture and the making of lattice-plane counts from cross-sectional HRTEM imaging of the reference features. This paper describes the design details and the fabrication of the cross-bridge resistor test structure. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross sections of the cross-bridge resistors' reference segments, as a prelude to making them available for dimensional reference applications     

Junction-isolated electrical test structures for critical dimension calibration standards

The National Institute of Standards and Technology (NIST) is developing single-crystal reference materials for use as critical dimension (CD) reference materials. In earlier work, the reference features on these reference materials have been patterned in the device layer of a silicon-on-insulator (SOI) wafers, with the buried oxide providing electrical isolation. This paper describes a new method of isolating the structures from the substrate by means of a pn junction. The junction isolation technique is expected to provide several advantages over the SOI technique including minimal susceptibility to charging when imaged in a CD scanning electron microscope (CDSEM), better edge quality, and ease of manufacture. Primary calibration of these reference materials is by imaging the cross-section of the feature with high-resolution transmission electron microscopy (HRTEM) at sufficiently high energy to resolve and count the individual lattice planes while electrical test structure metrology techniques provide the transfer calibration. Secondary calibration is performed with electrical test structure metrology, supplemented by visual techniques to verify that the features meet uniformity requirements. In this paper, we describe results for determining the electrical critical dimensions of these junction-isolated structures. This measurement and data analysis technique is a unique combination of the short-bridge variation of the cross-bridge resistor and the multi-bridge structure.     

Hybrid optical-electrical overlay test structure

This paper describes the exploratory use of electrical test structures to enable the calibration of optical overlay instruments of the type used to monitor semiconductor-device fabrication processes. Such optical instruments are known to be vulnerable to hard-to-determine systematic process- and instrument-specific errors known as shifts. However, these shift errors generally do not affect electrical test-structure measurements extracted from the same features. Thus the opportunity exists to configure physical standards having overlay targets that can be certified by electrical means, thereby enabling estimates of the shifts prevailing in a particular application. In this work, a new hybrid test structure, meaning one from which overlay measurements can be extracted electrically, as well as by optical instruments, has been designed and fabricated with built-in overlay values ranging from -60 to +60 nm. A selection of structures constituting a test chip has been patterned in a single conducting film with CD (critical dimension) design rules ranging from 1.0 μm to 2.0 μm and fabricated and tested. Electrical overlay parameters, derived from multiple step-and-repeat die-site measurements, generally match the corresponding optical measurements to within several nanometers, subject to limitations of the pattern-replication process. This paper focuses on the extraction of overlay from the electrical measurements, the dependence of the measurements on CD design rules, and their comparison with the corresponding measurements made both by a commercial optical-overlay instrument and by a coordinate-measurement system having measurements traceable to absolute dimensional standards. It is presented as a first step toward the use of electrical measurements for advancing shift management in optical overlay of features patterned in separate lithographic processes     

ZnO纳米棒的图形化生长及其场发射特性

介绍了用氢离子注入技术和阳极腐蚀方法在硼掺杂p-(100)型硅晶片上制备图形化的纳米硅(SiNC)薄膜工艺，并在这种图形化衬底上成功生长了图形化的ZnO纳米棒. 场发射测试表明制备的ZnO纳米棒具有良好的场发射性能，即具有较低的开启电场和阈值电场，较高的发射点密度.     

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO2) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO2laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm²/V sec and leakage currents < 10 pA, for a Channel length of 12 µm and width of 20 µm. Achievement of high-performance TFT's with the combined features of microcrack suppression, preferred orientation, and selected-area crystallization render CO2- laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.     

Crystallographic texture of C54 titanium disilicide as a function of deep submicron structure geometry

Detailed analysis of the crystallographic texture of C54 TiSi₂ was performed and showed a strong correlation between the geometry of the silicide structures and preferential crystallographic orientation. The study was undertaken on blanket and patterned TiSi₂ films formed in the reaction between 32 nm of Ti and undoped polycrystalline silicon using both in situ x-ray diffraction during heating and post-anneal four-circle pole figure reflection geometry measurements. Full pole figures were taken to determine the distribution of C54 TiSi₂ grain orientations in narrow (0.2 to 1.1 μm) lines which was compared with similar results obtained from unpatterned (blanket) films. While in blanket films we found the presence of weak <311> C54 TiSi₂ crystallographic orientation perpendicular to the sample surface, the <040> preferential orientation dominated in patterned submicron line structures and increased with decreasing linewidth. Using pole figure analysis, we observed strong <040> fiber texture in narrow lines with a slight variation in the tilt of the (040) planes normal in the direction perpendicular to the line (full width at half maximum [FWHM] ≈6°), but very little along the length of the line (FWHM ≈2°). In addition, a preferred in-plane (azimuthal) orientation of <040> crystals was found which showed that most of the <040> grains had their (004) plane normals oriented parallel with the line direction. These findings support a model of the C49 to C54 TiSi₂ transformation involving rapid growth of certain orientations favored by the one-dimensional geometry imposed by narrow lines.     

Test structures for referencing electrical linewidth measurements to silicon lattice parameters using HRTEM

A technique has been developed to determine the linewidths of the features of a prototype reference material for the calibration of critical-dimension (CD) metrology instruments. The reference features are fabricated in mono-crystalline-silicon with the sidewalls aligned to the (111) lattice planes. A two-step measurement procedure is used to determine the CDs. The primary measurement is via lattice-plane counting of selected samples using high-resolution transmission electron microscopy (HRTEM); the transfer calibration is via electrical CD (ECD) test-structure metrology. Samples of these prototype reference materials were measured and provided, as the National Institute of Standards and Technology (NIST) Reference Material RM8110, to International SEMATECH for evaluation by its member companies. In this paper, we will describe the measurement procedure and show how the combined uncertainty of less than 15 nm was derived. Additionally, we demonstrate a technique to automate the analysis of the phase-contrast images in order to both minimize the cost and reduce the uncertainty of the calibration of the standards.     

Noncontact critical dimension metrology sensor for chrome photomasks featuring a low-temperature co-fired ceramic technology

This paper describes a noncontact capacitive-sensor metrology sensor developed to measure minimum feature sizes, also called critical dimensions, patterned on photomasks that are used in semiconductor device manufacture. Additionally, this paper describes the test structures printed on photomasks that facilitate linewidth metrology with the new sensor. The metrology sensor is fabricated using a low temperature co-fired ceramic technology and its principle is based on noncontact microcapacitance measurements of features on chrome-on-glass reticles.     

Electrical measurement of submicrometer contact holes

A technique to measure submicrometer-sized isolated features electrically is described. P.M. Hall's formula (1967-8) modified with an experimentally determined coefficient is used to obtain the hole diameter and the hole area from the electrically measured linewidth with a higher precision than the precision of the linewidth itself. By incorporating a large number of features in a single test structure, a gain in precision of better than 3 nm is shown analytically. The contact hole diameter and the area of the isolated features obtained in this way, were found to be accurate when compared with physical measurements using a scanning electron microscope. The test pattern used is a combination of two basic four-point probe linewidth-measuring structures and two modified ones. The modified structures contain a large number of contact holes in the 10-μm lines running in the horizontal and vertical directions, which reduce the apparent electrical linewidth. Subtracting the reduced linewidth from that of a solid reference line removes the other contributions to linewidth variation. The size of the contact holes can then be derived from these results. The special test pattern, an analytic expression for interpretation of the results, and hole size data from a variety of exposure dosages are discussed     

Multilayer planarization of polymer dielectrics

Polymers are widely used in the microelectronics industry as thin-film interlevel dielectrics layers between metal lines, as passivation layers on semiconductor devices and in various packaging applications. As multiple layers of polymer and patterned metal are constructed, the ability of these polymers to planarize topographical features becomes increasingly important. In this study, the degree of planarization (DOP) for five commercially available polymers has been examined for three different structural configurations with the intent of simulating practical applications. Specifically, this study investigates single layer planarization, multiple coat planarization, and planarization of metal lines patterned on a polymer base. This study also examines the effects of orientation of the metal structure to polymer flow during spin casting and location on the wafer. The polymers are selected to investigate different polymer chemistries frequently used in the microelectronics industry. The underlying structures were fabricated using standard photolithography and electroplating techniques. Feature dimensions include 25-200 μm line spacings and widths with the polymer overcoat thickness being twice the height of the underlying structures     

The Race for the Photonic Chip: Colloidal Crystal Assembly in Silicon Wafers

This paper surveys recent developments in engineering physics approaches and self‐assembly chemistry methodologies for creating 3D photonic crystals and how this has led to in‐wafer patterned colloidal crystals. These materials are comprised of single crystal micrometer scale features of silica colloidal crystals that have controlled thickness, area, and orientation and are embedded within a single crystal silicon wafer. Two processes for growing opal‐patterned chips are described. One is based upon microfluidic and the other spin coating driven self‐assembly of colloidal silica micro‐spheres within a lithographic patterned silicon wafer.     

Defect-free silicon film on SiO2 formed by zone meltingrecrystallization with high scanning speed

The recrystallization of polysilicon films on silicon dioxide at high scanning speed, in the range of 5≈15 mm/s, with an RF-induced graphite strip heater system is discussed. The films are in (100) orientation and contain subgrain boundaries (SGBs). Heat-sink and valley structures have been used to localize these SGBs. Defect-free silicon films have been obtained with good uniformity and reproducibility. The differences between the results obtained with fast scanning and the conventional slow scanning is analyzed. n-channel and p-channel MOSFETs have been fabricated in the recrystallized silicon film to characterize electrical properties such as mobilities and leakage currents, and they show very good characteristics     

Si-YBaCuO intermixing and reactive patterning technique

A novel Si-YBaCuO intermixing technique has been developed for patterning YBaCuO superconducting thin films on both insulating oxide substrates (MgO) and semiconductor substrates (Si). The electrical, structural, and interfacial properties of the Si-YBaCuO intermixed system have been studied using resistivity, x-ray diffraction, scanning electron microscopy, x-ray photoelectron spectroscopy and Auger depth profiling measurements. The study showed that the reaction of Si with YBaCuO and formation of silicon oxides during a high temperature process destroyed superconductivity of the film and created an insulating film. On a MgO substrate, the patterning process was carried out by first patterning a silicon layer using photolithography or laser-direct-writing, followed by the deposition of YBaCuO film and annealing. For a silicon substrate, thin metal layers of Ag and Au were patterned as a buffer mask which defines the YBaCuO structures fabricated thereafter. Micron-sized (2-10 Μm) superconducting structures with zero resistance temperature above 77 K have been demonstrated. This technique has been used to fabricate current controlled HTS switches and interconnects.     

Low-Roughness Plasma Etching of HgCdTe Masked with Patterned Silicon Dioxide

A novel mask technique utilizing patterned silicon dioxide films has been exploited to perform mesa etching for device delineation and electrical isolation of HgCdTe third-generation infrared focal-plane arrays (IRFPAs). High-density silicon dioxide films were deposited at temperature of 80°C, and a procedure for patterning and etching of HgCdTe was developed by standard photolithography and wet chemical etching. Scanning electron microscopy (SEM) showed that the surfaces of inductively coupled plasma (ICP) etched samples were quite clean and smooth. Root-mean-square (RMS) roughness characterized by atomic force microscopy (AFM) was less than 1.5 nm. The etching selectivity between a silicon dioxide film and HgCdTe in the samples masked with patterned silicon dioxide films was greater than 30:1. These results show that the new masking technique is readily available and promising for HgCdTe mesa etching.     

Microstructural characterization of nickel hydroxide films deposited using an ammonia-induced method and subsequently calcined nickel oxide films

Nickel hydroxide films were deposited using a facile ammonia-induced method. The deposited films were composed of stacking structures without using templates or surfactants. The microstructures of the deposited films and subsequently calcined NiO films were characterized using X-ray diffraction, scanning electron microscopy and transmission electron microscopy. The electrical properties were also investigated. The deposited films consisted of triangular stacks of single crystal hexagonal Ni(OH)₂ and their microstructures were highly affected by the substrate type. A preference for orientation along the (001) plane was observed in the Ni(OH)₂ films deposited onto indium tin oxide (ITO) substrates with a high texture coefficient of 4.5. These characteristics were not found in Ni(OH)₂ films deposited onto glass and silicon substrates. Calcined films did not show a strong preference in orientation and were found to be n-type NiO.     

Large-Area Direct Hetero-Epitaxial Growth of 1550-nm InGaAsP Multi-Quantum-Well Structures on Patterned Exact-Oriented (001) Silicon Substrates by Metal Organic Chemical Vapor Deposition

We employ a simple two-step growth technique to grow large-area 1550-nm laser structures by direct hetero-epitaxy of III–V compounds on patterned exact-oriented (001) silicon (Si) substrates by metal organic chemical vapor deposition. Densely-packed, highly uniform, flat and millimeter-long indium phosphide (InP) nanowires were grown from Si v-grooves separated by silicon dioxide (SiO₂) stripes with various widths and pitches. Following removal of the SiO₂ patterns, the InP nanowires were coalesced and, subsequently, 1550-nm laser structures were grown in a single overgrowth without performing any polishing for planarization. X-ray diffraction, photoluminescence, atomic force microscopy and transmission electron microscopy analyses were used to characterize the epitaxial material. PIN diodes were fabricated and diode-rectifying behavior was observed.     

MOSFET's fabricated in laser-recrystallized Silicon on Quartz using selectively absorbing dielectrical layers

MOSFET's were fabricated in laser-recrystallized silicon islands on fused quartz substrates using a standard n-channel self-registered poly-gate process. Selective absorption obtained with patterned dielectric films was used to control the shape of the melt front during recrystallization of patterned LPCVD polysilicon islands. IR imaging of the laser-heated region was used to optimize and monitor the melt front shape. Devices with various channel lengths and widths were fabricated and the dependence of threshold voltage, channel mobility, and subthreshold leakage on recrystallization conditions and device dimensions were studied. Devices with and without back-channel implants were compared on the same wafer and for the same laser annealing conditions. The back-channel implant consistently reduced the subthreshold leakage to less than 1 pA/µm.